JPH01180024A - Control system for synchronous logic circuit - Google Patents

Abstract

PURPOSE:To decrease energy consumption of the title circuit being in a stand-by state by causing the oscillating frequency of a clock pulse oscillating means to be low while a synchronous logic circuit is in the stand-by state. CONSTITUTION:The logic circuit executes a logic processing with synchronizing to a clock pulse from an oscillating means 20 which is composed of an oscillating circuit 1 and a dividing circuit 3. The dividing circuit 3 extracts a standard clock signal CLKA from a terminal QA to supply to a line 4, and the signal is fed to an AND gate 5. Then, a low speed clock signal CLKB is extracted from a terminal QB and fed to the AND gate 5. The logic circuit executes back-up processing such as the reception of an input or a time processing but while in the standy state in which the original processing is not executed, the processing can be executed at low speed clock since the processing quantity is small. The higher a clock frequency becomes, the larger the energy consumption quantity becomes and the narrower the operating voltage range of the logic circuit becomes. Thus, AND gates 5 and 7 are selected through an FF8, and during in the stand-by state, the processing is executed with use of the low speed clock signal CLKB. Then, the energy consumption quantity is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention is suitable for microcomputers, etc. that require backup processing to standby for example, input reception, clock processing, etc. even when power is cut off during normal arithmetic processing. The present invention relates to a control method for a synchronous logic circuit implemented in the present invention.

BACKGROUND ART Traditionally, microcomputers have been known to shut off the power or use random access memory (RAM) when there is no need for backup processing such as input reception or clock processing during standby when arithmetic processing is suspended. In order to save power, power is supplied only to the However, when backup processing is required as described above, such backup processing consumes a considerable amount of power. Therefore, it is desirable to have a configuration that can reduce power consumption during standby while backup processing is performed. It had been.

Problems to be Solved by the Invention An object of the present invention is to provide a control method for a synchronous logic circuit that can reduce power consumption during standby.

Means for Solving the Problems The present invention provides a control method for a synchronous logic circuit that performs logic processing in synchronization with a clock pulse output from an oscillation means. This control method for a synchronous logic circuit is characterized in that the oscillation frequency of the oscillation means is lowered during standby when no processing is being performed.

According to the present invention, the logic circuit performs logic processing in synchronization with the clock pulse from the oscillation means.Furthermore, the logic circuit does not perform the processing that it should originally perform, such as accepting input or clock processing. During standby when backup processing is being performed, the amount of processing is smaller than during normal processing, and therefore processing can be performed even with a low-speed clock. Furthermore, the higher the tarok frequency, the greater the power consumption, and the narrower the operating voltage range of the logic circuit.

Therefore, the oscillation frequency of the oscillation means is lowered during standby, thereby making it possible to reduce power consumption during standby and widening the operating voltage range of the logic circuit.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. A constant frequency pulse signal CLK from an oscillation circuit 1 including a crystal oscillator 31 and activation circuits 32 and 33 is given via a line 2 to a frequency dividing circuit 3 realized by, for example, a counter. 1 oscillation circuit 1 and frequency divider circuit 3, 0 frequency divider circuit 3 constituting oscillation means 20 outputs standard clock signal CLKA from output terminal QA to line 4.
is derived and applied to one input of AND gate 5, and a low-speed clock signal CLKB is applied to line 6 from output terminal QB.
is derived and applied to one input of AND gate 7.

The signal CLK from the oscillation circuit 1 led out on line 2 is also applied to the clock input terminal CLK of flip 70 tube 8. The input terminal of this flip-flop 8 is
An output from OR gate 9 is given. When the power switch 10 is turned on, one input of the OR gate 9 receives a high level input from the power supply 15 from the resistor 11 and the buffer 12 via the line 17.

The output from the output terminal Q of flip-flop 8 is line 1.
3 to the other input of AND gate 5, and the output from output terminal Q is applied to A via line 14.
It is applied to the other input of ND gate 7. The output from the AND gate 5.7 is applied to the clock input terminal EX of the microcomputer 21, which is a logic circuit. This input terminal EX is connected via a resistor 22 to a battery 23 which is a backup power source. microcomputer 21
performs logical processing in synchronization with the clock signal input from the clock input terminal Eχ. The input terminal R of the flip-flop 8 is connected to a line 19 with different levels.

A reset signal generation circuit 24 is provided in association with the microcomputer 21, and the output from the reset signal generation circuit 24 is applied to the reset input terminal RESET of the microcomputer 21 via the line 18 and is inverted. Input terminal P of flip-flop 8
is input.

Also provided in connection with the microcomputer 21 are a read-only memory (hereinafter abbreviated as ROM) 25, a random access memory (hereinafter abbreviated as RAM) 26, and an input/output circuit 27. They are interconnected via address buses AO-Am, data paths DO-Dm, and control lines 28. Power from the battery 23 is supplied to the power input terminal VCC of the microcomputer 21 .

The RAM 26 is supplied with power from the battery 23,
Even if the power switch 10 is cut off by this,
Its memory contents are retained. The input/output circuit 27 is supplied with a signal equal to one input of the OR gate 9 representing the switching behavior of the power switch 10 via a line 17.29. Input/output circuit 27 is also connected via line 30 to the other input of OR gate 9.

The operation of the above-described frit tube flora 18 is shown in Table 1.

(Left below) Table 1 In Table 1, P is the inverted input of input terminal P,
That is, it represents the level of line 18, and R represents the inverted input of input terminal R, that is, the level of line 19. In this first table, * represents redundancy.

Therefore, when line 18, the inverting input P of input terminal P, is at a low level, the other input terminals, CL
Regardless of the states of K and R, the output terminal Q is at high level and the output terminal Q is at low level. Also line 19,
That is, when the inverted input R of the input terminal R is at a low level, the output terminal Q becomes a low level and the output terminal Q becomes a high level, regardless of the states of the other input terminals, CLK, and P.

When both the inverted inputs P and H of the input terminals P and R are at high level and the input terminal is at low level, the output terminal Q becomes low level by capturing the fall of the signal CLK shown by ↓, Output terminal Q becomes high level. Further, when the inverting inputs P and R are at a high level and the input terminal is at a high level, the fall of the signal CLK is captured and the output terminal Q becomes a high level, and the output terminal Q becomes a low level.

FIG. 2 is a waveform diagram for explaining the operation.

When the signal CLK from the oscillation circuit 1 is shown in FIG.
The clock signal CLKA shown in figure (2) is derived,
Further, a clock signal CLKB shown in FIG. 2(3) is derived from the output terminal QB to the line 6.

At time t1, when the power switch 10 is turned on as shown in FIG. 2 (4), the flip-flop 8 is turned on in synchronization with the signal CLK, and the output terminal Q is turned on as shown in FIG. 2 (5). The output terminal Q becomes a high level, and the output terminal Q becomes a low level as shown in FIG. 2 (6). As a result, the clock input terminal E of the microcomputer 21
As shown in FIG. 2 (7), there is an AND gate 5 at X.
When the standard clock signal CLKA is inputted to the microcomputer 21, the microcomputer 21 can carry out the normal processing that it should normally perform, such as a tuning operation if the microcomputer 21 is used in a radio device.

Further, at time t2, when the power switch 10 is cut off as shown in FIG. 2(4), the flip-flop 8
In synchronization with the signal CLK, the output terminal Q is set to a low level as shown in FIG. 2 (5), and the output terminal Q is set to a high level as shown in FIG. 2 (6). As a result, the clock input terminal EX of the microcomputer 21
As shown in FIG. 2 (7), a low-speed clock signal CLKD is inputted through the AND gate 7, and it is possible to perform backup processing such as accepting input and clock processing, and then stand by.

In this way, during backup processing of the microcomputer 21, processing is performed using the clock signal CLKB, which is slower than during normal processing, making it possible to reduce power consumption and create a margin in the operating voltage range. You can have it.

In the above explanation, when the power switch 10 is not conductive, the input terminal of the flip-flop 8 is at a low level and backup processing is performed. When the input/output circuit 27 detects that one input of the OR gate 9 has become a low level, the microcomputer 21 outputs an output to the input/output circuit 27 by software, and outputs the other input of the OR gate 9 via the line 30. The clock signal CLK is configured to be at a high level and is the same as in normal processing.
Processing may be performed in A.

Effects As described above, according to the present invention, while the logic circuit is on standby,
Since the oscillation frequency of the oscillation means is lowered, power consumption during standby can be reduced and the operating voltage range of the logic circuit can be widened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. 1... Oscillation circuit, 3... Frequency dividing circuit, 5.7... A
ND gate, 8...flip-flop, 9...OR
gate, 10... power switch, 20... oscillation means, 21... microcomputer, 23... battery,
24... Reset signal generation circuit, 25... ROM,
26...RAM, 27...Input/output circuit agent patent attorney number of strokes Keiichi

Claims (1)

[Claims] In a control method for a synchronous logic circuit that performs logic processing in synchronization with a clock pulse output from an oscillation means, the synchronous logic circuit performs the processing that the synchronous logic circuit is supposed to perform. 1. A control method for a synchronous logic circuit, characterized in that the oscillation frequency of the oscillation means is lowered during standby.