JPH0358207A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce power consumption as a whole by providing a selection circuit which selects and outputs one of plural system clocks from a frequency division circuit, and enabling the system clock supplied to each functional unit to be selected. CONSTITUTION:An oscillation circuit 1 oscillating with a prescribed frequency, the frequency division circuit which frequency-divides an oscillation clock from the oscillation circuit 1 and generates plural system clocks CL1-CL4, and the select9ion circuits 31A-31N which select and output one of the system clocks CL1-CL4 with a write signal WR from a CPU 4 according to written data are provided. Furthermore, plural functional blocks 3A-3N provided with internal circuits 32A-32N operated with the system clocks outputted from the selection circuits 31A-31N correspondingly, and perform prescribed functions are provided. Thereby, it is possible to supply the system clock suitable for each functional unit, and to reduce the power consumption as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a microcomputer equipped with an internal system clock generation circuit.

[Conventional technology]

A microcomputer configured with complementary MOS (hereinafter abbreviated as CMOS) has a characteristic that the power consumption of the microcomputer increases as the speed of the system clock signal used internally increases. To this end, measures have been taken to reduce the overall power consumption by slowing down the speed of the system clock supplied to specific functional units within the microcomputer.

A program diagram showing an example of a conventional microcomputer is shown in FIG. 5, and a waveform diagram of its clock signal is shown in FIG.

Multiple functional units} 3a to 3n, central processing unit 4A (hereinafter abbreviated as OPU4A), oscillation circuit 1, and oscillation clock C
In a microcomputer that has a frequency dividing circuit 2A that divides LO into a plurality of system clocks CL1 and CL2, the divided low frequency system clock CL2
is supplied to a specific functional unit} 3a, and a high frequency system clock CL1 is supplied to other functional units 3b to 3n including the CPU 4A.
By reducing the power consumption of the microcomputer, the overall power consumption of the microcomputer was reduced. Furthermore, even if either the system clock CLI or the system clock CL2 is stopped, the functional units that supply the system clock that is not stopped can continue to operate.

[Problem to be solved by the invention]

However, in the conventional microcomputer described above, since the system clock supplied to each functional unit 3a to 3n is fixed, a high frequency system clock is supplied even to functional units that do not require high-speed operation. It is impossible to select a system clock when there is a problem that the system clock is running at high speed or low speed during operation depending on the functional unit. The problem is that you can't choose.

An object of the present invention is to provide a microcomputer that can supply a system clock suitable for each functional unit and reduce overall power consumption.

[Means to solve the problem]

The microcomputer of the present invention includes an oscillator circuit that oscillates at a predetermined frequency, a frequency divider circuit that divides the output signal of this oscillation circuit to generate a plurality of system clocks each having a different frequency, and a frequency divider circuit that generates a plurality of system clocks each having a different frequency. The system has a selection circuit that selects and outputs one of the plurality of system clocks, and a plurality of functional blocks each having an internal circuit operated by the system clock from the selection circuit and performing a predetermined function.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, the oscillation clock CL is transmitted at a predetermined frequency.
An oscillation circuit 1 that outputs the clock signal CLO, a frequency divider circuit that divides the oscillation clock CLO from the oscillation circuit 1 to generate a plurality of system clocks OL1 to CL4 each having a different frequency, and a frequency divider circuit that generates a plurality of system clocks OL1 to CL4 having different frequencies, and Selection circuits (31A to 31N) that write data internally and select and output one of the system clocks CLI to CL4 according to the written data;
A plurality of functional blocks 3A to 3N each having a corresponding internal circuit (32A to 32N) operated by a system clock output from a system clock (31N) and performing a predetermined function,
A selection circuit 41 writes data DT internally in accordance with the write signal WR from the internal circuit 42, and selects and outputs one of the system clocks aL1 to CL4 according to the written data DT, and from this selection circuit 41. The system includes an internal circuit 42 that operates according to an output system clock, and a CPU 4 that performs predetermined functions.

FIG. 2 shows an oscillation clock CLO and this oscillation clock C
System clock CLI~C generated by frequency dividing LO
A waveform diagram of L4 is shown.

FIG. 3 is a circuit diagram showing a specific example of the selection circuits 31A to 31N, 41 of this embodiment.

Each register REGI, REG2 of the register circuit 311 receives data DT (consisting of DTI, DT2) from the data bus 5 in response to a write signal WR from CPTJ4.

) is written.

The contents of register 8 REG1 are “0” and register REG2
When the content of the inverters INI and IN2 is "0", the outputs of the inverters INI and IN2 become 1.') Among the AND gates ANI to AN4, only AN4 becomes 1, and T. of the transfer gates TRI to TR4 becomes 1. Only R1 is turned on, and the system clock CLI is selected as the system clock CLK in the functional unit.

Similarly, when register REGI is "1", register REGI
When G2 is "0", the system clock CL2 is set to register REGI, and when register REG2 is "1", the system clock CL3 is set to registers REGI, RE.
When both G2 are 11111, system clock CL4
is selected.

In this first embodiment, the system clock sources are OLI to CL4, but even n system clock sources can be selected in the same way by using m registers (n≦2''') and decoding them. It is clear that

FIG. 4 is a circuit diagram showing a selection circuit according to a second embodiment of the present invention.

The selection circuit of this second embodiment is an RO that can be changed with a mask pattern instead of the register circuit 3110 of the first embodiment.
A ROM circuit 312 including MI and ROM2 is provided, and the ROM circuit 312 allows the user to select in advance the system clock to be used for each functional unit. Therefore, since there is no need to write data DT, there is an advantage that the circuit becomes simpler.

〔Effect of the invention〕

As described above, by making it possible to select the system clock supplied to each functional unit, the present invention can supply a system clock suitable for the operating speed of the functional unit, thereby reducing overall power consumption. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 and 3 are waveform diagrams of the oscillation clock and system clock according to the first embodiment of the present invention, and a circuit diagram showing a specific example of the selection circuit, respectively, and FIG. 4 is a selection circuit according to the second embodiment of the present invention. FIGS. 5 and 6 are a block diagram showing an example of a conventional microcomputer and a waveform diagram of its clock signal, respectively. 1...Oscillation circuit, 2,2A...Divide circuit, 3A to 3N. 3a~3n・・・Functional unit}
, 4, 4A...CPU, 5...Data bus, 31A-31N...Selection circuit, 42A-4
2...Internal circuit, 4l...Selection circuit, 42...Internal circuit, 311...Register circuit, 312...ROM circuit , ANI~A
N4...AND gate, INI, IN2...
...Inverter, TRI~TR4: ...Transfer.

Claims (1)

[Claims] An oscillation circuit that oscillates at a predetermined frequency, a frequency divider circuit that divides the output signal of this oscillation circuit to generate multiple system clocks each having a different frequency, and a frequency divider circuit that generates multiple system clocks each having a different frequency. 1. A microcomputer comprising: a selection circuit that selects and outputs one of the selection circuits; and a plurality of functional blocks each having an internal circuit operated by a system clock from the selection circuit and performing a predetermined function.