JP2623833B2 - Clock advance control system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clock advance control system, and more particularly, to a selective clock advance control system that selectively controls a clock supply to an internal block in a mounting module for an information processing apparatus.

Prior art Selective clock advance control in an information processing device
This is effective for scan-in and scan-out control using a scaffold having an F / F (flip-flop) chain configuration and partial diagnostic control in an information device. When implementing such scan-in / scan-out control, in a small information processing apparatus having a small number of F / Fs, scan-in / scan-out control may be performed within the apparatus as a scan path configuration of one F / F chain. In information processing devices such as large computers and supercomputers with a very large number of F / Fs,
Unless the speed of scanning specific registers and control F / Fs is increased to some extent, the performance of initial setting and logout will be affected. Therefore, it is common to divide the inside of the apparatus into a plurality of blocks and provide a scan path for each block. When the apparatus has a plurality of scan paths as in the latter case, it is necessary to perform clock advance control in block units including the selected scan path.

Partial diagnosis control in the device is performed by an information processing device such as a large-scale computer or supercomputer with a very large amount of hardware.If a diagnosis is performed on the entire device, the execution time becomes extremely long. When the range to be diagnosed can be limited to some extent by an error indicator as in the case of time, it is very efficient if the diagnosis can be performed only on that part.

It is best if the partial diagnosis can be performed in units of the above-described block in units of the scan path, but usually, it is often performed over a plurality of adjacent blocks. This is because it is easy to make a diagnosis for each functional unit of hardware. Therefore, in the partial diagnosis in the apparatus, clock advance control is required for a plurality of selected blocks.

As a method for implementing the clock advance control for one or a plurality of blocks selected as described above, a clock advance selection register having bits corresponding to a clock signal to be distributed to each block is prepared. A method of advancing only a clock signal corresponding to a bit set valid in the above is widely adopted.

In recent years, the mounting technology of information processing devices has been improved, and the degree of integration has been improved. It is possible to mount multiple blocks that can constitute a scan path, and furthermore, a mounting module that has a distribution circuit inside to supply a clock to each block. Is being developed and becoming popular. For an information processing device composed of mounting modules with such a mounting structure,
An example in which clock advance control is realized using the above-described clock advance selection register will be described below.

The information processing apparatus shown in FIG.
And a clock supply circuit 2 and mounting modules 3 to 5 having main functions.

Each of the mounting modules 3 to 5 has four internal blocks and a two-input gate circuit for clock distribution. The mounting module 3 includes internal blocks 3a, 3b, 3c and 3d and corresponding two-input AND gates 30a, 30b for clock distribution.
It has 30c and 30d. Each internal block has one scan path of F / F chain configuration.
Not shown in the figure.

The mounting modules 4 and 5 have the same configuration as the mounting module 3, and the mounting module 4 includes internal blocks 4a, 4b, 4c and 4d and two-input AND gates 40a, 40b and 40c for clock distribution.
And 40d, and the mounting module 5 has an internal block 5
a, 5b, 5c and 5d and two-input AND gate 50 for clock distribution
a, 50b, 50c and 50d are present.

The clock supply circuit 2 is a circuit that supplies a clock to the mounting modules 3 to 5 and the maintenance diagnosis processor 1,
FIG. 2 shows only the clock supply circuits of the mounting modules 3 to 5. The clock oscillator 22 is a common clock oscillator of the mounting modules 3 to 5, and its output, that is, a clock signal is input to the mounting modules 3 to 5 by the distribution buffer gates 210 to 212, respectively.

After the output clock signal of the buffer gate 210 is input to the mounting module 3, a two-input AND gate 30 for clock distribution is provided.
Input is connected to the first input terminal of each of a, 30b, 30c and 30d. Similarly, the output clock signals of the buffer gates 211 and 212 are two-input AND gates 40a, 40b and 40c for clock distribution, respectively.
And 40d, and two inputs for clock distribution and two input AND gates 50a, 50b, 50c and 50d. The maintenance diagnosis processor 1 includes mounting modules 3 to
5 is a processor for performing maintenance diagnosis, but FIG. 2 shows only the controller 16 and the clock advance control circuit.

The F / F 14 is a 1-bit flip-flop for setting a mode for supplying a clock to all the internal blocks included in the mounting modules 3 to 5 (all clock supply mode). It is specified and updated (set / reset) by the instruction of the controller 16. F /
The output signals of F14 are OR gates 10a to 10d, 11a to 11d and 12a.
12d are connected to the first input terminals.

Each of the registers 17 to 19 has a 4-bit configuration, and is a clock advance selection register corresponding to four internal blocks existing in the mounting modules 3 to 5, respectively. register
17 to 19 are updated by the instruction of the controller 16, and the registers 17 to 19 are updated.
The outputs of bits 17a, 17b, 17c and 17d of the OR gates 10a,
The second input terminal of 10b, 10c and 10d is connected to the bit of register 18
The outputs of 18a, 18b, 18c and 18d are supplied to the second input terminals of the OR gates 11a, 11b, 11c and 11d, respectively.
The outputs of 9c and 19d are connected to the second input terminals of the OR gates 12a, 12b, 12c and 12d, respectively.

OR gates 10a, 10b, 10c and 10d are mounted module 3
Is a gate circuit that generates and outputs a clock enable signal corresponding to the internal blocks 3a, 3b, 3c, and 3d. The output of the OR gates 10a, 10b, 10c and 10d is
2 input gates 30a, 30b, 30c and 3 for clock distribution inside
The input is connected to the second input terminal of 0d.

The OR gates 11a, 11b, 11c and 11d are mounted module 4
Is a gate circuit that generates and outputs a clock enable signal corresponding to the internal blocks 4a, 4b, 4c, and 4d. The outputs of the OR gates 11a, 11b, 11c and 11d are respectively
2 input gates 40a, 40b, 40c and 4 for clock distribution inside
The input is connected to the second input terminal of 0d.

The OR gates 12a, 12b, 12c and 12d are mounted on the mounting module 5
Is a gate circuit that generates and outputs a clock enable signal corresponding to the internal blocks 5a, 5b, 5c, and 5d. The outputs of the OR gates 12a, 12b, 12c and 12d are respectively
2 input gates 50a, 50b, 50c and 5 for clock distribution inside
The input is connected to the second input terminal of 0d.

Next, the clock advance control in the above configuration will be described. When the clock advance control is performed, there are the following three cases.

(1) Clock advance control when performing normal operation (2) Clock advance control when performing scan-in / out operation in units of internal blocks (3) Clock advance control when performing internal diagnosis (1) In order to supply a clock to all the internal blocks of the mounting modules 3 to 5, the controller 16 clears all bits of the registers 17 to 19 to 0, sets the F / F 14 and sets the mode to the all clock supply mode.

In the case of (2), a clock is supplied to one internal block selected from the internal blocks of the mounting modules 3 to 5, and scan-in / out of the internal block is performed. Therefore, the controller 16 resets the F / F 14, and registers 17 to 17 corresponding to the desired internal block.
Set one bit in 19

The partial diagnosis in the case of (3) is executed for each of the mounted functions of the mounting modules 3 to 5 shown in FIG. Therefore, the controller 16 resets the F / F 14, and registers 17 to 17 corresponding to one or a plurality of internal blocks having a desired function.
Set the bit in 19.

Accordingly, the setting combinations of the registers 17 to 19 satisfying the above cases (1) to (3) are as shown in FIG.

In the information processing apparatus configured with the mounting modules as described above, the functions to be subjected to the partial diagnosis are generally used for reasons such as reducing the machine cycle and increasing the speed, and reducing the hardware division loss as much as possible. Are often mounted in one mounting module. In addition, there is no advantage even if it is constituted by a plurality of mounting modules.

Therefore, the pattern for setting the clock advance selection register for performing the partial diagnosis can be relatively small. However, since the clock selection register of the related art has independent bits for each internal block, it is possible to set many combinations that cannot be subjected to partial diagnosis. By preparing bits in units of internal blocks in this way, all variations are possible, but if the number of mounted modules and internal blocks becomes large, it is necessary to prepare a considerable amount of hardware as a clock selection register There is a major drawback of doing so.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock advance control system capable of reducing the amount of hardware of a clock selection register.

According to the present invention, a clock advance of an information processing apparatus including m (m is a natural number of 2 or more) mounting modules each having n (n is a natural number of 2 or more) internal blocks is provided. A control system, comprising: a clock signal supply unit that supplies one clock signal to each of the m mounting modules; and a validity / invalidity of the clock signal from the clock supply unit for each of the plurality of mounting modules. First clock control means for controlling, and clock distribution means provided corresponding to each of the m mounting modules and distributing the clock signal supplied to the mounting module to each of the n internal blocks And validity of the clock signal distributed by the clock distribution means.
And a second clock control means for controlling invalidation for each of the n internal blocks.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The information processing apparatus shown in FIG. 1 includes a maintenance diagnosis processor 1, a clock supply circuit 2, and mounting modules 3 to 5 having main functions.

Each of the mounting modules 3 to 5 has four internal blocks and a two-input gate circuit for clock distribution. The mounting module 3 includes internal blocks 3a, 3b, 3c, and 3d and corresponding two-input AND gates 30a, 30b, and 30c for clock distribution.
And 30d. Each internal block is provided with one scan path having an F / F chain configuration, but is not shown in FIG.

The mounting modules 4 and 5 have the same configuration as the mounting module 3. The mounting module 4 includes internal blocks 4a, 4b, 4c and 4d and two-input AND gates 40a, 40b and 40c for clock distribution.
And 40d, and the mounting module 5 has an internal block 5
a, 5b, 5c and 5d and 2-input AND gate 50 for clock distribution
a, 50b, 50c and 50d are present.

The clock supply circuit 2 is a circuit that supplies a clock to the mounting modules 3 to 5 and the maintenance diagnosis processor 1,
FIG. 1 shows only the clock supply circuits of the mounting modules 3 to 5. The clock oscillator 22 is a common clock oscillator of the mounting modules 3 to 5, and its output, that is, a clock signal is a 2-input AND gate 210 to 212 for distribution.
Is input connected to the first input terminal of

The two-input AND gates 210 to 212 for distribution supply a clock signal to the mounting modules 3 to 5, respectively, and the output clock signal of the two-input AND gate 210 for distribution is input to the mounting module 3 and then the two-input AND gate 30a for clock distribution. , 30b, 30
The input is connected to the first input terminal of each of c and 30d.

Similarly, the output clock signals of the two-input AND gates 211 and 212 for distribution are respectively two-input AND gates 40 for clock distribution.
Inputs are connected to first input terminals of a, 40b, 40c and 40d, and first input terminals of two-input AND gates 50a, 50b, 50c and 50d for clock distribution, respectively.

The OR gates 200 to 202 are gate circuits that generate and output clock enable signals corresponding to the mounting modules 3 to 5, respectively, and are connected to the second input terminals of the two-input AND gates 210 to 212 for distribution.

The maintenance diagnosis processor 1 is a processor that performs maintenance diagnosis of the mounted modules 3 to 5, and FIG. 1 shows only the controller 16 and the clock advance control circuit.

The F / F 14 is a 1-bit flip-flop for setting an all clock supply mode for supplying a clock to all the internal blocks included in the mounting modules 3 to 5, and when "1", specifies the all clock supply mode. Updated by the instruction of the cotton roller 16. The output signal of F / F14 is OR gate 10a ~
The input is connected to the first input terminals of 10d, 11a to 11d and 12a to 12d, and is also connected to the second input terminals of the OR gates 200 to 202 of the clock supply circuit 2 via the buffer gate 15.

The register 13 is a clock advance selection register of all 7 bits, a 3-bit field of bits 130 to 132 is a clock enable corresponding to the mounting modules 3 to 5, and output signals thereof are OR gates 200 to 200 of the clock supply circuit 2, respectively. The input is connected to the second input terminal 202.

Also, the 4-bit field of bits 13a to 13d is the internal block 3a to 3d of the mounting module 3, the mounting module 4
Corresponding to the internal blocks 4a to 4d and the mounting modules 5a to 5d, respectively, and the output signal of the bit 13a is output from the OR gates 10a and 10a.
The output signal of bit 13b is applied to the second input terminals of 1a and 12a, and the output signal of bit 13b is applied to the second input terminals of OR gates 10b, 11b and 12b.
Is output to the second input terminals of the OR gates 10c, 11c and 12c, and the output signal of the bit 13d is output to the OR gates 10d, 11d and 12d.
Are respectively connected to the second input terminals. Register 13
Is updated by the instruction of the controller 16.

The OR gates 10a, 10b, 10c and 10d are gate circuits for generating and outputting clock enable signals corresponding to the internal blocks 3a, 3b, 3c and 3d of the mounting module 3. The output of the OR gates 10a, 10b, 10c and 10d is the mounting module 3 respectively.
2 input gates 30a, 30b, 30c and 3 for clock distribution inside
The input is connected to the second input terminal of 0d.

The outputs of the OR gates 11a, 11b, 11c and 11d are two-input gates for clock distribution 40a, 40b,
The input is connected to the second input terminals of 40c and 40d.

The OR gates 12a, 12b, 12c and 12d are gate circuits for generating and outputting clock enable signals corresponding to the internal blocks 5a, 5b, 5c and 5d of the mounting module 5. Or gate
The outputs of 12a, 12b, 12c and 12d are connected to the second input terminals of two input gates 50a, 50b, 50c and 50d for clock distribution inside the mounting module 5, respectively.

Next, with the above configuration, the mounting modules 3 to
The clock advance controller for the 5 internal blocks will be described.

In the case of the normal operation of (1), the controller 16 clears all bits of the register 13 to 0, sets the F / F 14 and sets the mode to the all clock supply mode.

In the case of the scan-in / out operation of (2), the controller 16 resets the F / F 14 to include one of the bits 13a to 13d of the register 13 corresponding to the desired internal block and the desired internal block. One of the bits 130 to 132 of the register 13 corresponding to the mounting module is set.

In the case of the partial diagnosis operation of (3), the controller 16
F14 is reset, and the bits in bits 13a to 13d of the register corresponding to one or more internal blocks having the desired function shown in FIG. 3 and the register corresponding to the mounting module including the internal block 13 bits 130-1
Set one bit of 32.

Therefore, the setting combinations of the register 13 satisfying the above cases (1) to (3) are as shown in FIG.

A comparison between FIG. 4 and FIG. 5 shows that in the case of FIG. 5 using the present invention, a desired operation can be realized with a clock advance selection register having a small number of bits.

Effects of the Invention As described above, according to the present invention, by providing the clock advance selection control means for each mounting module and the clock advance selection control means for each internal block common to each mounting module, a small amount of hardware is provided. Has a great effect that a scan-in / out operation or a partial diagnosis operation can be executed.

Using the number m of mounted modules and the number n of internal blocks,
Expressing the number of bits of the clock advance register,
(M × n) bits in the prior art, and (m + n) in the present invention
And the prior art is (3 × 4)
= 12 bits, the present invention is (3 + 4) = 7 bits,
The effect becomes more remarkable as the number of m and n increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional technique, FIG. 3 is a diagram showing functions of internal blocks in FIGS. 1 and 2, and FIG. FIG. 5 is a diagram showing an example of clock advance control in a conventional example, and FIG. 5 is a diagram showing an example of clock advance control in an embodiment of the present invention. Description of Signs of Main Parts 1 ... Maintenance Diagnosis Processor 2 ... Clock Supply Circuit 3,4,5 ... Installed Module 3a-3d ... Internal Block 4a-4d ... Internal Block 5a-5d ... Internal Block 13 ... … Register 16 …… Controller

Claims (3)

(57) [Claims] 1. A clock advance control system for an information processing apparatus comprising m (m is a natural number of 2 or more) mounting modules each having n (n is a natural number of 2 or more) internal blocks. A clock signal supply unit that supplies a clock signal of one system to each of the m mounting modules; and a first unit that controls the validity / invalidity of the clock signal from the clock supply unit for each of the plurality of mounting modules. Clock distribution means provided corresponding to each of the m mounting modules, and distributing the clock signal supplied to the mounting module to each of the n internal blocks; Second clock control means for controlling the validity / invalidity of the clock signal distributed by the distribution means for each of the n internal blocks. Clock advance control system according to claim. 2. The method according to claim 1, wherein the first clock control means specifies a mounting module for which the clock signal is valid, and
2. The clock advance control system according to claim 1, wherein the clock control means specifies one of the internal blocks in the specified mounting module that makes the clock signal valid. 3. The clock signal supplied to the corresponding mounting module, wherein the first clock control means includes m flip-flops corresponding to each of the mounting modules. The second clock control means includes n flip-flops corresponding to each of the internal blocks, and each of the n flip-flops is supplied to the corresponding internal block. A signal indicating whether the clock signal is valid among the internal blocks is designated by a combination of the setting of the m flip-flops and the setting of the n flip-flops. The clock advance control system according to claim 1, wherein