GB2137847A - Picture Image Processing System - Google Patents

Abstract

A picture image processing system is constructed of a plurality of operation modules (M1 ... M3) adapted to process image data in accordance with their respective operation routines, a common data bus (6) for feeding the image data to the operation modules and clock- generating means (8) for producing data input/output signals at a specific timing which controls the transfer of data between the operation modules and the data bus and divides the bus cycle. The operation modules are controlled to process the image data in any selected desired sequence. Owing to the time-sharing only a single bus is necessary. <IMAGE>

Description

SPECIFICATION Picture Image Processing System This invention relates to a picture image processing system which is reconfigurable and is adapted to process a two dimensionally-arrayed picture image.

Picture image processing systems are roughly divided into fully parallel systems, pipe-line control systems, locally parallel systems, multiprocessor systems, etc. in accordance with their processing manners and configurations.

Many of currently-employed picture image processing systems cannot however be clearly classified into either of the above-described various types. They are, in many instances, formed of combinations of two or more of such different types of systems, because each of the above-mentioned systems has both merits and demerits.

In the fully parallel system, each of its basic operation modules is arranged into the same twodimensional structure as picture elements. The operation modules can be operated parallelly so as to process data on all the picture elements simultaneously. Therefore, the fully parallel systems has materialized high-speed processing.

This fully parallel system can exhibit the -merit of high-speed processing when the system is constructed using units-or devices, which have been designed exclusively to process binarycoded picture images and expect to receive binary-coded data as picture image data, or employing specificallysdesigned LSl processors or the like adapted to perform specifically-limited processings only. However, it requires to provide processors as many as the number of picture elements of a picture image. Thus, its circuit connection becomes enormous, leading to a difficulty in manufacturing actually-usable systems. Therefore, the fully parallel system is not generally employed.

In the pipe-line control system, a plurality of basic operation modules are arrayed in series, for example as illustrated in Fig. 1. In this case, one processing step is divided into processing substeps of a certain time unit. Some continuous data strings are processed in such a way-that they are input per every time unit so as to obtain outputs continuously after a certain delay time period.

The pipe-line control system permits highspeed processings despite of its simple configuration and may be constructed of ICs and LSls which are generally available on the market.

However, conventional pipe-line control systems were accompanied by such a drawback that they lacked of versatility as to the processing order of picture image data and did not have flexibility in configuration.

In a structure formed for example of basic operation modules M1, M2, M3 connected together as depicted in Fig. 1, an input data D, is first of all processed at the module M1 and is then caused to pass through the modules M2, M3 to obtain and output D2. Since the order in which the input data D1 is to be processed is fixed, it will become indispensable to add a data pass route indicated by dashed lines in Fig. 1 for example if one wants to process the input data D1 using the modules1, M2, M3 in the order of M1#M3#M2 so as to obtain an output D2,.

If many operation modules are included and the picture image data are of an 8-bit structure of graded signals, the system will become tremendously large even by its wirings only. Thus, its actual utilization is difficult in many instances.

The locally parallel system is a compromise between the fully parallel processing system and the pipe-line control system. It is constructed by connecting a circuit designed exclusively for local processing and a scanning control circuit adapted to perform the local processing successively all over the picture, to a picture image memory. Here, arithmetic operations are by themselves performed principally by the pipe-line control system and data, which are to be subjected to operations, are stored in the picture image memory and the memory access is controlled in priority by software, with a view toward solving the difficulty of the circuit structure in an actual system. However, the locally parallel system has the same level of shortcoming as the preceding two systems, with respect to its structural flexibility.

With a view toward permitting free selection of processing order, there has also been proposed such a ring bus system as illustrated in Fig. 2 in which a data bus is formed of a ring bus. This system permits to connect the operation modules M1, M2, M3 in accordance with the type of processing of picture image data while allowing to perform the control of the connection with flexibility.

According to the data transfer method making use of the ring bus system illustrated in Fig. 2, each picture image data is fed out to the bus b after labelling same with an ID code. The data is then input from the bus to an operation module designated by the ID code, for example, to the operation module M2. Upon completion of processing of the picture image data at the module M2, the resulting image data is labelled with another ID code which indicates the next module M3 and is then output to the bus b.

It is thus possible to determine the order of use of operation modules by applying such ID codes one after another in the above manner, thereby imparting flexibility to the connection through the modules.

In the above-described ring bus system, picture image data are however successively input one after another from the bus and, after completion of their processings, are output successively one after another. Therefore, it is necessary to improve the processing speed of each operation module per se if one wants to increase the processing speed.

Supposing now that the transfer clock supplied to the bus b has a period T, a time period nT is required to apply n types of operations to a single piece of picture image data (see, Fig. 3). When the above system is adopted for a picture image processing system which is used to process a picture image containing many picture elements and is equipped with separate operation modules respectively for different types of processings, a data is output for the first time from the memory to the bus b when the processings of its preceding data by all the operation modules have been fully completed. Therefore, the above system was accompanied by a drawback that the overall processing time becomes longer in proportion to the required number of operations n.

Consequently, the pipe-line control system is advantageous from the viewpoint of processing time because it requires only a certain extent of delay and output data are successively obtained with a certain interval of processing time upon a elapsed time of the certain extent of delay if the processing time in each operation module is set at the same time period and it is thus free of the integration effects of operation time periods which integration effects occur in the ring bus system.

With the foregoing in view, the present invention has as its object the provision of a reconfigurable picture image processing system which permits to use its operation modules in any desired order by using a single data bus while making use of the merit of the pipe-line control system.

In one aspect of this invention, there is thus provided a picture image processing system which comprises a plurality of operation modules adapted to process image data in accordance with their respective operation routines, a common data bus for feeding the image data to the operation modules and clock-generating means for producing data input/output signals at a specific timing which controls the transfer of data between the operation modules and the data bus and divides the bus cycle, which operation modules are controlled to process the image data in a desired sequence.

The picture image processing system of this invention has brought about the following advantages: (1) A single bus is employed to pass picture image data. Input/output of data to/form each operation module are performed at a timing which corresponds to the processing time period, in other words, divides the bus cycle further.

Owing to this time-sharing use of the bus, the efficiency of data transfer has been improved and the pipe-line control system has been successfully incorporated.

(2) The reconfiguration is of the presetting type, namely, may be conducted by allocating the timing clock suitably. Thus, it is unnecessary to label individual picture image data with ID codes.

(3) It is possible to reconfigure the system in such a way that the number of time-divided timing pulses, which are contained in a single bus cycle, can be changed by the number of operation modules to be employed to perform processings.

Owing to this feature, a simple processing operation may be performed promptly.

The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings.

In the accompanying drawings: Fig. 1 is a block diagram showing a conventional picture image processing system of the pipe-line control system; Fig. 2 is a block diagram illustrating a conventional picture image processing system of the ring bus system; Fig. 3 is a timing chart showing transfer of data between operation modules in a ring bus system; Fig. 4 is a block diagram of a picture image processing system according to one embodiment of-this invention, which system has been connected to a memory disk and host computer; Fig. 5 is a timing chart illustrating the bus cycle of the system of Fig. 4; Fig. 6 is a block diagram depicting one example of the operation modules in the system of Fig. 4; Fig. 7 is a block diagram showing one example of operation modules in a system similar to that shown in Fig. 4 except that two timing buses have been employed;; Fig. 8 is a timing chart illustrating one example of the bus cycle in the system of Fig. 7; Fig. 9 illustrates the operation of an nrepresentation counter by way of example; and Fig. 10 is a block diagram showing one way to provide an additional data bus.

Embodiments of this invention will hereinafter be described with reference to the accompanying drawings.

In Fig. 4, a disk memory 1 contains picture image data obtained by sampling a picture pattern and quantizing same.

A host computer 2 serves to operate individual basic operation modules 41, 42, 43 ~ . ., in accordance with a program which is provided to use a picture image processing system 3 in its entirety. The operation modules 41. 42 43 ~ ~43,...

have their own picture image processing functions which are independent from one another, and are adapted for example to perform affine transformations for gradation correction and enlargement, reduction, rotation and the like of picture images, the so-called dot etching in which a certain constant value is either added to or subtracted from each data as routinely practiced in photomechanical processes, and arithmetic and logical operations such as syntheses of picture images.

The picture image processing system 3 is connected to the host computer 2 via an interface 5. Numeral 6 indicates a data bus. The operation modules #i 41, 43,... are commonly connected to the data bus 6 so that they can receive or send out data independently through the data bus 6. In order to give specific operating instructions to the modules 41. 42, 43 ~ . ., a presettable control unit such as a microcomputer 7 is also connected to the data bus 6. Since it is advantageous to use a microcomputer as such a presettable control unit, the embodiment of this invention will be described in detail while using such a microcomputer by way of example.

Numeral 8 indicates a timing generator, which is connected not only to the microcomputer 7 but also to a timing bus 9 which is adapted to supply timing pulses to the modules 41, 42, 43,. ... The microcomputer 7 is connected to a ,u-CPU bus 10 so as to preset timing setting values respectively to the modules 41, 42, 43,....

In the thus-constructed picture image processing system 3, data or instructions are first of all transferred from the host computer 2 to the microcomputer 7, whereby to interrupt the microcomputer 7. The thus-transferred data or instructions permits the microcomputer 7 to determine what processing will first be performed on which data. In accordance with the thus-made decision, timing-setting values are preset respectively to the modules 41, 43,43 The details of such presetting values will be described later in this specification.

On the other hand, the picture image data stored in the disk memory 1 are fed to the data bus 6 by way of the interface 5, wherby to perform the input of data to the operation modules 41. 42, 43,... and the output of the resulting processed data to the bus in synchronization with the timing pulses.

The presetting of the timing-setting value will next be described.

The principal feature of this invention resides in that input/output of data from/to a data bus is performed using a plurality of timing pulses which time-divides each by cycle. The presetting is required to determine which one of the timings is to be used.

Fig. 5 illustrates timing pulses produced at the timing generator 8 and fed respectively to the operation modules 41. 42, 43,... by way of the timing bus 9.

In order to make the description simpler, let's now assume that four timing pulses P1, P2, P3 P4 are given respectively to the four basic operation modules (i.e., n=4). In other words, description will be made on a method in which a bus is used by time-dividing the basic bus cycle T with four pulses (n=4).

The data passing sequence through the basic operation modules is M1#M3#M3#M4. A new data is always kept in the interface. Data are always output from the interface whenever their corresponding preceding data have been input to the operation module M1. On the other hand, the operation module M4 does not output data but receives processed data one after another and stores them therein for example like a buffer memory.

At the timing generator 8, masking pulses PM2, PM3, PM4 which are adapted to control initial stages are formed together with timing pulses P1, P2, P3 based on instructions from the microcomputer 7, whereby instructing the operation sequence through the modules 41, 42, 43,44. The masking pulses PM2~PM4 serve to protect initial data and are not specifically required if an initial part of a data string is discarded.

Namely, P1-P4 are output by the start pulse P5 in Fig. 5. At this time point, the data which has been output from the interface and is present on the data bus 6 is introduced into the operation module 41 by the first clock of the timing pulse P1.

The data is then processed there and is thereafter transferred to the operation module 43 by the first clock of P4.

In accordance with the second clock of P1, the operation module 41 receives the next new picture image data and perform an arithmetic operation on the thus-received picture image data.

With respect to the timing pulses P1-P4 produced relative to the basic bus cycle T by timedivision techniques, P1 is allocated to input data to the module M1, P3 is allocated to output data from the module M3 and to input data to the module M4, P3 is allocated to output data from the module M3 and to input data to the module M3, and P4 is allocated to output data from the module M1 and to input data to the module M2.

The arithmetic operation is performed in a time period w3T Namely, the time period (n--l)n is the maximum processing time. Here, the last operation module does not produce any outputs.

In this case, the bus cycle T is n . t.

As apparent from Fig. 5 and the above description which has been made with reference to Fig. 5, the system of the above embodiment includes the modules M1-M3 as modules adapted to perform arithmetic operations. The total processing time reaches (4-1 )x3t=9t.

Namely, the thus-processed data reaches the module M4 upon an elapsed time of 9t and has then been taken in the module M4 upon an elapsed total time of (9+1)xt (i.e., 2.5T).

In Fig. 5, PM2, PM3, P M4 are masks which inhibit inputs to their corresponding operation modules M2, M3, M4. The operation module M3 outputs data when P4 and PM3 have been both input. Data are output from the operation module M3 when both P3 and PM3 have been input. On the other hand, the operation module M4 outputs data when P3 and PM4 have been both input.

The operation modules input and output data as shown in Fig. 5.

Fig. 6 illustrates one example of an operation control circuit provided with the same construction to each of the basic operation modules 41, 42 43 ~ The data bus 6 is connected to an operation circuit 13 by way of an input gate 1 1 and input latch 12, so that picture image data may be input to the operation circuit 1 3. The operation circuit 1 3 is designed in such a way that processed picture image data are output to the data bus 6 via an output latch 14 and output gate 1 5.

The YCPU bus 10 is connected to an input side preset latch circuit 1 6 and an output-side preset latch circuit 1 7. These preset latch circuits 1 6, 17 are set to determine whether the operation modules 41 42, 43,. .. receive preset from the microcomputer 7 preset data on which one of the timing pulses P1, P2, P3, P4 is to be used or the operation modules 41, 4Z, 43,... output processed data. This determination is made by the microcomputer in accordance with only the program stored in the microcomputer or inputs from a key board or the like.

The preset latch circuit 1 6 is connected to a decoder 1 8, the decode output terminals of which are connected respectively to the input terminals of AND gates 191,192, 193, 193, 194. On the other hand, the output terminals of the AND gates 191, 192 1 93, 1 94 are all connected to the input terminals of an OR gate 1 95. The output terminal of the OR gate 1 95 is connected as the output terminal of a GATE circuit 1 9 to the aforementioned input gate 11 and input latch 12.

The timing bus 9 is constructed of buses 91, 92 93,94 adapted to supply the timing pulses P1, P2, P3, P4 and buses 95, 96 97 adapted to feed the masking pulses Pom2, Pom3' P M4 The bus 91, buses 928 97, buses 93, 9,, and buses 94, 95 are connected respectively to the AND gate 1 91 AND gate 1 92Z AND gate 193 and AND gate 1 94. Each output of the decoder is timing-controlled at the gate circuit 1 9.

Similar to the input-side preset latch circuit 1 6, the output-side preset latch circuit 17 is connected to a gate circuit 21 via a decoder 20.

To the gate circuit 21, the timing pulses Pa, Pz, P3, P4 and masking pulses Pom3, PM3, PM4 are fed from respective buses of the timing bus 9.

Let's now suppose by way of example that the presetting value to the input-side preset latch circuit 1 6 from the microcomputer 7 is 00. This presetting value is decoded to a 4-bit figure of 0001 at the decoder 18. This 4-bit figure is used directly as inputs to the gates 19,--19,. Thus, only the gate 1 91 is input and, as a result, the input gate 1 1 and latch 12 are operated in synchronization with the timing bus 91" By the way, the gate circuit 21 is of the same structure as the input-side gate circuit 1 9 and its detailed description is thus omitted.

When the operation modules 41, 43,43,... are constructed in the above manner and the preset latch circuits 1 6, 17 are set for example in such a manner that picture image data are input in accordance with the timing pulse P1 and processed picture image data are output in accordance with the timing pulse P4, the start pulse P5 is fed to the timing generator 8 so as to produce the pulses P1, P2, P3, P4. Thus, the output of the gate circuit 1 9 takes an H (high) level at the first clock of the pulse P1, thereby inputting picture image data from the data bus 6 to the input latch 12.

Thereafter, the data are processed in accordance with a prescribed operation routine at the operation circuit 1 3 and then transferred to the output latch 1 4.

The processing time in the operation circuit 13 is the maximum (3t). In the initial stage, the timing pulse P4 opens the gate circuit 21 for the first time when the masking pulse PM3 is supplied at the H l level to the gate circuit 21. By an output from the decoder 20, picture image data are output from the output latch 14, through the output gate 15, and to the data bus 6.

From the next stage, the operation circuit 13 is operated only by Px, without being affected by PMX.

Namely, the operation modules 41,42,43, 43,...

are allowed to process picture image data in a desired sequence provided that timing-setting data have been input in advance to the preset latch circuits 1 6, 17 from the ,u-CPU bus 10.

In this case, it is feasible to determine, in accordance with the number of operation modules required to process picture image data, how many timing pulses P1, P3,... should be used to divide a single cycle of the basic clock.

The timing generator 8 can divide timing pulses as desired, for example by means of a programmable counter or the like.

If picture image data do not synchronize with the speed of the basic clock for example when the picture image data are transferred from the disk memory 1 or host computer 2 so as to input the picture image data for the first time to the operation modules 41.42,43, ~ . . or when processed picture image data are stored back to the disk memory 1, the clock of the timing circuit 8 may be stopped by the timing of the interface 5.

Fig. 7 illustrates another embodiment of this invention, in which two timing buses are employed.

In Fig. 7, an operation module which is surrounded by a dashed line is connected to two timing buses 22, 23, in addition to the data bus 6 and y-CPU bus 10.

The operation module is formed of such a circuit as will be given below. Namely, there are illustrated in Fig. 7 a preset latch circuit 24, an nrepresentation counter 25 for input, an nrepresentation counter 26 for output, decoders 27, 28, an input latch 29, and operation circuit 30, an output latch 31 and an output gate 32.

In this embodiment, the timing buses 22, 23 have been simplified. The timing buses 22,23 are respectively fed with clocks CK1, C K3 shown in Fig. 8, so that data input/output signals are produced in their respective operation modules.

The preset latch circuit 24, has, in advance, been set with a time-division cycle number n-1, an input timing signal kin and an output timing signal kout delivered from the microcomputer 7 by way of the ,u-CPU bus 10, so that n--l and kin are supplied to the input side n-representation counter 25 while n-1 and kout are fed to the output-side n-representation counter 26.

Fig. 8 is a timing chart when n=4, kin=3 and kout=2.

The input-side n-representation counter 25 will next be described.

Fig. 9 shows one example of the input-side n representation counter 25, in which the input-side n-representation counter 25 is constructed of a synchronous counter 33 and an equality circuit 34.

When CK2 is at "H" level, kin is loaded to the counter 33 during a rise time of CK 1. kin becomes count data (output) of the counter 33. At the next time of the CK1, the count data is increased by 1 at the counter 33. In this manner, the counter 33 operates to increase its count data one by one during each rise time of CK1.

Each output of the counter 33 is input to the equality circuit 34. To the other input terminal of the equality circuit 34, (n-1) is input. When the count data of the counter 33 coincides with (n-1), the equality circuit 34 takes an "H" level which is input to the clear terminal of the counter 33. When another rise time of CK1 is input to the counter 33, the output data of the counter 33 is reduced to zero.

In the above manner, the counter 33 is operated at each rise time of CK1 and outputs 0, 1, 2 .

n-i as its output data, in other words, operates as an n-representation circuit.

The decoder 27 receives outputs from the input-side n-representation counter 25 and outputs data successively as Cin 0, Cin 1,. .. as depicted in Fig. 8.

Cin 0 latches data from the data bus 6 to the input latch 29 at each rise time thereof.

Cin 1 and Cin 2 are internal timings employed in the operation circuit 30 and may not be required depending on the contents of each operation. The operation circuit 30 starts processing simultaneously with the latching of data to the input latch 29 and finishes the operation until Cin n-2. It latches results to the output latch 31 at each rise time of Cin n-i.

The output-side n-representation counter 26 has the same structure as the input-side nrepresentation counter 25 and is present similar to the above-described embodiment. In this case, it is only necessary to give a timing which simply turns on the output buffer 32 when outputting a signal from the output-side n-representation counter. The decoder 28 performs decoding only when the output of the output-side nrepresentation counter 26 is turned to ~ and thus turns on the output gate 32.

The n-representation counters 25, 26 are used for the following reasons. Namely, there are both long and short operations. The setting of n is carried out for shortening the overall operation time by making n equal to the longest operation among a group of operation modules required for each operation. When the operation is short, the output latch 31 retains the operation results at Cin n-m Jnd outputs it to the data bus when Count 0 occurs. However, the operation results also keeps to hold the operation results (i.e., the holding of the operation results continues until next Cin n-m).

The time-divided input and output operations are performed in the above manner.

Fig. 10 illustrates by way of example a bus expansion method when many operation modules 41 43,43,.. are connected.

When many operation modules 41 42, 43 are connected to a single data bus 6, the buffering capacity of the output gate may become unable to drive all the loads connected thereto. Namely, even if the fan-out has exceeded the ability of an element, it may be possibla to provide still more operation modules with the same timing provided that data from the bus 61 is transferred to the bus 63 while using a specific operation module 4n merely as a latch circuit.

As has been described above, the present invention permits to reconfigure the internal structure of a picture image processing system in accordance with the nature of processing of picture image data and, at the same time, to perform a variety of picture image processings within the operation speed of the usual TTL system.

A processing speed of a certain high level is required for example when processing a picture image by means of a layout scanner employed generally in the photomechanical process while displaying resulting picture images on a color monitor. Such a processing speed can be achieved by connecting operation modules into the pipe-line control system. Since the system of this invention requires only one data bus, its wiring work is easy and its structure is simple.

Moreover, it is unnecessary to provide more wiring when more operation modules are added.

The present invention can improve the picture image processing performance, especially, in a layout scanner which contains a number of operation models.

Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the invention as set forth herein.

Claims (8)

1. A picture image processing system, comprising a plurality of operation modules adapted to process image data in accordance with their respective operation routines, a common data bus for feeding the image data to the operation modules and clock-generating means for producing data input/output signals at a specific timing which controls the transfer of data between the operation modules and the data bus and divides the bus cycle, which operation modules are controlled to process the image data in a desired sequence.

2. The picture image processing system as claimed in Claim 1, wherein the clock-generating means is constructed of a timing generator adapted to produce time-divided pulses which divide the basic clock by N and a gate circuit adapted to select data input/output signals from the time-divided pulses at each of the operation modules, so that image data are input to n units of the operation modules in a single cycle of the basic clock.

3. The picture image processing system as claimed in Claim 1, wherein the sequence in which the image data are to be processed is program-controlled in accordance with the timings of data input/output signals produced respectively by the operation modules.

4. The picture image processing system as claimed in Claim 2, wherein the sequence in which the image data are to be processed is program-controlled in accordance with the timings of data input/output signals produced respectively by the operation modules.

5. The picture image processing system as claimed in Claim 1, wherein the clock-generating means is constructed of a timing bus adapted to feed a common bus cycle and a bus cycle clock, which is N times the bus cycle, to each of the operation modules and a clock-generating circuit adapted to produce data input, data processing and data output timing pulses for each of the operation modules.

6. The picture image processing system as claimed in Claim 1, wherein the clock-producing means is constructed of a timing bus adapted to feed a common basic clock and a bus cycle clock, which has a cycle N times the basic clock, to each of the operation modules and an operation control circuit adapted to form data input/output signals respectively at the operation modules in accordance with preset timing selection data.

7. The picture image processing system as claimed in Claim 1, wherein the system further comprises a bus transmitter when the system contains more operation modules, whereby to reduce the fan-out of each gate or buffer.

8. A picture image processing system substantially as hereinbefore described with reference to and as illustrated in Figures 4 to 10 and the accompanying drawings.