JPS5819973A - Multiprocessor computer of time division bus system - Google Patents

Abstract

PURPOSE:To perform the time division control which does not cause bus lock, by connecting two or more processors to a common bus through a bus use controller which controls the use of the common bus in respect to time. CONSTITUTION:N-number of processors P1, P2-Pn are connected to a common bus 2 through a bus use controller 1 which controls them to give the common bus use in time division. The bus use controller 1 gives the bus use to processors P1, P2-Pn in time division. The processor to which the use is given can not only monopolize the bus 2, a shared memory 3, and a shared input/output part 4 but also access other processors during this time. Thus, processors are controlled efficiently without causing bus lock.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor computer that uses a common path in time division.

Conventionally, computers with multiple processors have a method in which the number of paths is equal to the number of processors, and the connection between the paths is controlled by a cross-perswitch mechanism, and control is performed by determining the priority of path use rights for each process. There are various methods, but the former involves a large increase in the amount of hardware compared to the increase in the number of processes, while the latter causes the problem of pass lock, in which usage rights are hardly handed over to low-priority processes. There was a system configuration problem that needed to be resolved.

The present invention uses a relatively simple hardware configuration and allocates the right to use a common bus to each process in a time-sharing manner.
The present invention provides a multiprocessor computer that solves the above drawbacks.

The present invention provides control for dividing at least two processors, one common bus, and the right to use the common bus among the processors in terms of the number of processors, and allocating the divided time to each processor. It is characterized by having a path usage right controller that performs the following. .

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of the present invention is shown in FIG.

n processors Pz, ..., Pn, a bus right controller l that controls giving the right to use the common path to each processor in a time-sharing manner, a common bus 2, and each processor. It includes a memo 13 that can be shared and input/output M4 that can be shared by each process.

The bus right controller 1 has processes, Ps, Pg, . . .
....

Pn and the common bus 20, tpi in FIG. 2a.

Each period subscript Pi denoted by tpt---tpry,
Pg, ..., processor PI corresponding to Pn,
The right to use the bus is given to Pg, . . . -, and PnK. Processor ptd is given the right to use the period passes t@~t3 and t-~t4 shown in FIG. 2, and the common bus 2.
By making the shared memory 3 and the shared memory @4fPl exclusive, it is possible to access any processor other than processor P1. Similarly, as shown in Figure 2C, the process is h-%-1.
In the same way, the right to use the bus is given to each processor up to the processor Pa (FIG. 2d). Furthermore, when one processor is given the right to use the bus, it is controlled not to give the right to use the path to any other processor.

In this embodiment, the problems of multiprocessing errors caused by the conventional Talospar switching mechanism and multiprocessors caused by a method of determining and controlling processor priorities can be solved with relatively simple hardware.

As explained above, the present invention divides at least two or more processors, one common bus, and a bus usage right controller by temporally dividing the bus usage rights of these processors into the number of processors. 9,
This solves the disadvantage of the crossbar switching method, which is the increase in the amount of hardware due to the increase in the number of processors, and the problem of pass lock, which is the problem of the method of determining and controlling the priority t' of bus usage rights for each process. effective.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a time chart illustrating the operation of the bus right controller shown in FIG. 1...Bus usage right controller, 2...--Common bus, 3...--Common memory, 4...Military input/output unit.

Claims (1)

[Claims] A time-division path multi-channel bus system having at least two processors, one common A bus, and a bus usage right controller that controls the right to use the common bus for these processors based on time. processor calculator.