JPS6031649A - Timer controlling method in virtual computer system - Google Patents

Abstract

PURPOSE:To reduce the overhead of a virtual computer control program and to improve the accuracy of a timer by using the timer to execute the CPU timer processing of the virtual computer. CONSTITUTION:For a specific virtual computer VM, CPU timers (VM timers) 16-19 to be exclusively used for the VM, steps for executing start/stop of the timers, assigning to the specific VM and releasing the assignmant and a step for checking the assigning state of the timers are prepared. Since the CPU timer control processing for the VM is executed by using the VM timers 16-19, it is unnecesary to consider VM dispatching time slice processing by the virtual computer control program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a timer control method in a virtual computer system, and particularly relates to a specific virtual computer.
Suitable when PU timer accuracy is required.

[Background of the invention]

In a virtual computer system, each virtual machine (VM)
(7) The hardware interface is realized by a virtual machine controller program (VMCP) VC. VMCP manages computer resources (central processing unit, main storage device, input/output device, etc.) so that they are shared by each VM, and creates an environment in which each VM appears to occupy one real computer.

A timer is a resource shared by each VM. Timers include time-of-day (TOD) clocks, clock comparators, CPU timers, and interval timers.
In the MCP, a simulation is performed so that these timers are given to each VM as virtual timers.

The CPU timer, which is one of the timers, measures the elapsed time of the CPU, and when a preset time elapses.
This is a timer that is a means of generating an interrupt, and when the CPU is in a state where it can execute instructions (while the CPU is running, in a wait state, or during initial program loading)
The CPU timer is characterized by being updated at the same rate, in synchronization with the TOD clock, which shows a consistent elapsed time for time display purposes, but not otherwise: It is set to a certain value by the 5TPT (STore C
The current value is read by the PU Timer) instruction.

Also, during operation, it counts by 11' every 1 μs.
Generates an interrupt when it is down and becomes a negative value.

The M1 diagram shows an example where the count progresses to 52 μs in the case of 64 μs.

In the conventional method, the VMCP uses only one CPU timer in this system, and the VMCP and each VM
In order for each to operate as if it had its own CPU timer, it must be controlled so that they are shared in a time-sharing manner. The VMCP processes for this purpose include the following.

+Time slice control VMC for IIVM dispatch
P gives a certain amount of CPU time to each VM, and when that time is exceeded, it gives a time limit for deactivating other VMs.
Slice processing is performed, and a CPU timer is used as a means for this.

(2) Realization of virtual CPU timer The VMCP controls the real CPU timer in order to make it appear as if each VM has its own CPU timer. The processing for this purpose is as follows.

(a) Simulation of write/read commands issued from VM to virtual CPU timer from VM to SP
When a privileged instruction such as T,5TPT instruction is issued, v
MCP performs simulation of these instructions.

Figure 2 shows the actual CP when an SPT instruction is issued in a VM.
The data flow set in the U timer is shown. 1 is the real CPU timer, 20 to 2n are the VMs placed on the main memory
The time that CP uses to dispatch VMs.
These are the slice value and the virtual CPU timer value of each VM.

When the VMm shown in 3 issues the 8PT command, the VMm virtual CPU timer value 2m on the main memory is updated, and at the same time, the remaining time of the time slice value assigned by the VMCP to the VMm is calculated, and the 8PT command is updated. The value is updated. Then, the updated time slice value and the virtual CPU timer value for vMm are compared, and the smaller value is used for the real CPU.
Set in the PU timer.

Regarding 5TPT, which is a CPU timer read command, the current value as a virtual CPU timer is reflected.

When the system is equipped with a virtual machine assistance mechanism (VMA), these processes are processed at high speed by micro programs.

(b) Reflection of virtual CPU timer interrupt to VM When a CPU timer interrupt occurs, the interrupt first enters VMCP. The V'MCP determines whether the interrupt is for a time slice or a virtual CPU timer, and if it is a virtual CPU timer interrupt, a CPU timer interrupt is generated for the corresponding VM.

As mentioned above, the management of the CPU timer in a virtual machine is such that one real timer is shared between the vMCP and each VM, and the overhead required for time-sharing switching of the real timer is a problem. It became. Since the performance of a virtual machine is improved by reducing the processing time of VMCP, it has become necessary to reduce the overhead of CPU timer control by conventional methods.

In addition, since the timer is shared with other VMs, problems related to timer accuracy are likely to occur, such as timer errors due to switching of the real timer and delays in virtual CPU timer interrupts.
It became necessary to take measures.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems in a virtual computer system, reduce the VMCP overhead required for CPU timer control for a specific virtual computer, and improve the accuracy of the timer.

[Summary of the invention]

In the virtual computer system of the present invention, for a certain VM, a CPU timer dedicated to that VM, its start/stop,
The system includes a step of allocating and canceling allocation to a specific VM, and a step of checking the timer allocation status, and the timer is used to perform CPU timer processing for the VM.

[Embodiments of the invention]

Hereinafter, it will be explained in detail using examples.

The VM-dedicated CPU timer (hereinafter referred to as VM timer) of the present invention will be explained using FIG.

In Figure 3, 1 is the data indicated by the operand of the S'PT instruction issued by the VM, 2 is the register that stores the mask for starting/stopping the VM timer, 3 is the timer ID register, and 4 to 11 are AND circuits. , 12-15 are data gates, and 16-19 are VM timers.

Register 2 that stores the mask for starting/stopping the VM timer
each bit corresponds to each VM timer, and if the bit is '1', the corresponding V
The M timer is started and synchronized with the CPU timer and is sicant-downed, but when -0/, it is stopped. In this example, the second . The third bit is 1
', the VM timers 17 and 18 become operational.

Register 3, which indicates the VM timer corresponding to the currently running VM, is used to indicate the VM timer that the VM should use. Similar to register 2, register 3 has bits for each VM.
It corresponds to a timer. In FIG. 3, the third bit of register 3 is 1/, so when the data gate 14 is opened and the 8PT instruction is issued on 7M, the data content 1 pointed to by the operand is set only in the VM timer 18. Ru.

The VM timer has the same format as the existing CPU timer, but
The two points that differ from the CPU timer are that each VM timer has its own unique interrupt code and that the timer can be started/stopped by instructions. In this embodiment, four VM timers'f are provided, but the optimal number of VMs may be set as necessary.
Just set a timer.

The VM timer is activated when the corresponding VM is in running state or
The VM is made to operate only when it is in a waiting state, and is stopped otherwise.

This is a simulation of the situation in which the CPU timer operates in a real computer in a virtual computer environment. Loading/store to the VM timer start/stop register is performed by a dedicated instruction used only by the VMCP.

The VMCP allocates the VM timer to each VM.

When a VM to which a VM timer is assigned is dispatched, only the bit representing the corresponding VM timer in the timer ID register 3 is set to ``1''. Running VM is SPT/5TP
When issuing the T instruction, the corresponding bit of the timer ID register is '1' and only the VM timer that is in operation is accessed. VMs with no VM timer assigned
When dispatching, by setting all bits of the timer ID register to O, the virtual CPU using the conventional method
Performs timer control. Load/store of this register is also
This is done through dedicated load/store instructions used only by the MCP.

During operation, the VM timer counts down at fixed time intervals like the CPU timer, and generates an interrupt when the value becomes negative. Each VM timer has its own unique interrupt code. Interrupt to VMCP, 9, VMCP
reflects the interrupt to the corresponding VM.

Figure 4 shows the VM timer and existing CP when using this method.
Figure 3 shows the data flow for the U timer.

In Fig. 4, 111 to 11m-1 indicate the VM timer, and 2
00 indicates the existing CPU timer. VM timer 111-1
1m-1 are assigned to vM1 to VMm-1, respectively. 30 to 3n are data placed on the main memory,
3o is the time slice value performed by VMCP, 31 to 3n
represent virtual CPU timer values corresponding to VMm to VMn, respectively.

As shown in this figure, for the VM to which the 7M timer is assigned, the VMCP uses a timer different from the existing CPU timer used for time slice processing for VMff chair batching, so the 7M timer is There is no need to consider time slice processing when loading/reading. Regarding the existing CPU timer, the 7M timer is shared by the VM and VMCP to which it is not allocated.

〔Effect of the invention〕

With this method, a VM to which a dedicated CPU timer is assigned has the following advantages.

Since there is no need to consider metatimeslice processing for VM dispatch by ill VMCP, the simulation processing of STP and S'TPT instructions issued by the VM is simplified, and the speed of VMA can be increased.

(2) Since one VM can exclusively use the real timer, there is no need for timer switching processing in time division, and the efficiency of the timer can be improved.

(3) Since each 7M timer has a unique interrupt code, 7M timer
interrupt delays can be prevented.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the format of the CPU timer, which is one of the timers used in conventional virtual computer systems, and FIG. 2 is an explanatory diagram showing the format of the CPU timer, which is one of the timers used in conventional virtual computer systems. It is a block diagram showing a flow. FIG. 3 is an embodiment of the VM-dedicated CPU timer (7M timer) according to the present invention. FIG. 4 is a data flow diagram for the 7M timer and the existing CPU timer in the present invention.

Claims (1)

[Scope of Claims] 1. In a virtual computer system that allows multiple operating systems to run simultaneously on one real computer, a specific virtual computer is in a running state and a waiting state. A dedicated timer mechanism that operates at certain times and the steps to start/stop it,
A timer control method in a virtual computer system characterized by having a step for checking the allocation status of a timer, a step for performing allocation and deallocation to a specific VM. 2.The VM-dedicated timer is set to a specific VM by the management program.
is allocated to the VM, is activated only when the VM is in operation, and can only be written/written by instructions issued by the VM.
The timer is read and counted at regular time intervals, and when it reaches a certain value, it generates an interrupt with an interrupt code specific to the timer, and when the timer does not reach the specified value, the timer is controlled by the management program. Claim 1 characterized in that the device is placed in a stopped state by
Timer control method in the virtual computer system described in Section 2.