JPS61201326A - Information processor - Google Patents

Abstract

PURPOSE:To perform arithmetic processing and input/output editing processing in parallel by allowing a control processor and an input processor to handle an arithmetic memory in the same memory space with a control memory. CONSTITUTION:A memory request from the control processor 2 is selected by a multiplexer 11 and led to a demultiplexer 12. When a memory address is less than M, the memory request is sent to the control memory 4 and when more than M, the memory request is sent to the arithmetic processor 5; and the value M of a border register is subtracted and the memory request is sent to the arithmetic memory 6. Then access of the arithmetic processor 5 to the control memory access is initiated by an instruction processing unit 51, led to the multiplexer 11 of a system controller 1, and sent out to the control memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed arithmetic unit in an information processing device, and particularly to its system configuration.

[Problems to be solved by conventional technology and invention]

Conventionally, two types of high-speed arithmetic processors are known: an independent processor type and an attached processor type.

Although independent processor-type high-speed arithmetic units achieve high speed through highly parallel arithmetic mechanisms such as vector arithmetic,2 normal program execution is difficult to parallelize, such as input/output and associated editing processing. The problem was that the parallel processing mechanism did not work effectively when such parts were being executed.

Attached processor-type high-speed arithmetic units have high-speed arithmetic memory suitable for high-speed arithmetic operations, but data must be transferred between the arithmetic memory and control memory using channels etc. for input/output processing, making it difficult to use. The drawback was that it was difficult.

[Means for solving problems]

An object of the present invention is to eliminate the above drawbacks by configuring a high-speed arithmetic unit with a control processor and an arithmetic processor, and by making the arithmetic memory visible to the control processor and the input/output processor as the same memory space as the control memory. Another object of the present invention is to provide an information processing device that can perform arithmetic processing and input/output editing processing in parallel.

The information processing device of the present invention is a system control device.

A control processor, an input/output processor connected to it,
Equipped with an arithmetic processor and control memory.

An arithmetic memory is connected to the arithmetic processor, and the control memory and the arithmetic memory are seen as one memory space from the control processor and the input/output processor,
From the arithmetic processor, the control memory and the arithmetic memory are viewed as different spaces. The arithmetic processor has a boundary register that holds the capacity of the control memory, and in response to the arithmetic memory request from the system control device, sets a value obtained by subtracting the boundary address from the request address as the address of the arithmetic memory. It is configured.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, a system control device 1 includes a control processor 2 and an input/output processor 3 as a first processor group, and an arithmetic processor 5 as a second processor group.

They are each connected to a control memory 4 as a first memory. An arithmetic memory 6 serving as a second memory is connected to the arithmetic processor 5 . Memory requests from the control processor 2 and the input/output processor 3 are sent to the control memory 4 or the arithmetic processor 5 via a multiplexer 11 and a demultiplexer 12. A boundary register 10 is connected to the demultiplexer 12 . The control memory request of the instruction processing unit 51 inside the arithmetic processor 5 is connected to the multiplexer 11 of the system control device 1, and the arithmetic memory request is connected to the multiplexer 53. An arithmetic memory request from the system control device 1 is connected to the arithmetic memory 6 through a subtracter 52 and a multiplexer 53 in the arithmetic processor 5 . Another input of the subtractor 52 is:

Connected to boundary register 50. Write data and read data required to complete the memory access are not shown in the figure. Also, other units such as an arithmetic unit within the arithmetic processor 5 are not shown in the figure.

The following description will be made assuming that the capacity of the control memory 4 is M and the capacity of the calculation memory 6 is N. The memory requests of control processor 2 are selected by multiplexer 11 and routed to demultiplexer 12 . In the demultiplexer 12, the memory address is compared with the value M in the boundary register 10, and if the memory address is less than M, a memory request is issued to the control memory 4.

If the memory address is M or more, a memory request is issued to the arithmetic processor 5. In the arithmetic processor 5, the value M of the boundary register is subtracted from the request address by the subtracter 52, and the memory request is sent to the arithmetic memory 6 via the multiplexer 53. Memory requests from the input/output processor 3 are processed in the same manner.

Control memory accesses of the arithmetic processor 5 are issued from the instruction processing unit 51 and directed to the multiplexer 11 of the system control device 1 . and.

Processed similarly to control processor 2 memory requests.

It is sent to control memory 4. An arithmetic memory request issued from the instruction processing unit 51 is directly sent to the arithmetic memory 6 via the multiplexer 53.

As shown in FIG. 2, from the control processor 2 and the input/output processor 3, the control memory 4 and the calculation memory 6 are seen as one memory having an address space with a capacity of M+H.

The control processor 2 and the input/output processor 3 are connected to the control memory 4.
Since there is no need to be conscious of the distinction between the input/output and input/output editing, programming of input/output and input/output editing is easy. Since the control memory 4 and the arithmetic memory 6 appear to be different memories to the arithmetic processor 5, the arithmetic memory 6 can be designed independently of the control memory 4 in a form suitable for high-speed arithmetic.

〔Effect of the invention〕

As explained above, the present invention is a system that executes arithmetic processing and input/output editing processing in parallel by configuring the control processor and the input/output processor so that the arithmetic memory appears in the same memory space as the control memory. This has the effect that it can be easily provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram partially showing an embodiment of the present invention;
FIG. 2 is a diagram showing the address spaces of the control memory 4 and the arithmetic memory 6 in FIG. 1. 1... System control device, 2... Control processor. 3...I/O processor, 4...Control memory, 5.
... Arithmetic processor, 6... Arithmetic memory, 10...
Boundary register, 11...Multiplexer, 12...
Demultiplexer, 50... Boundary register, 51...
- Instruction processing unit, 52...subtractor, 53...multiplexer. 〜 −−

Claims (1)

[Claims] 1. A system control device, a first processor group, a second processor group, and a first memory connected thereto, and a second memory in the second processor group. In the connected information processing device, the first memory and the second memory are seen as one memory space from the first processor group, and the first memory and the second memory are seen from the second processor group. An information processing device characterized in that the second memory is configured to be viewed as a different memory space. 2. The second processor group has a boundary register that holds the capacity of the first memory, and in response to a request from the system control device to the second memory, the value of the boundary register is determined from the request address. 2. The information processing apparatus according to claim 1, wherein the address of the second memory is a value obtained by subtracting . 3. The system control device has a boundary register that holds the capacity of the first memory, and in response to a request from the first processor group to the second memory, the system control device reads the value of the boundary register from the request address. 2. The information processing apparatus according to claim 1, wherein the information processing apparatus is configured to send a value obtained by subtracting .