JPS60195660A - Dma controlling circuit system - Google Patents

Abstract

PURPOSE:To improve the processing speed and processing efficiency of a CPU, by providing a memory for direct memory access in an I/O channel board and directly performing memory access transfer without passing through a system bus. CONSTITUTION:In an I/O channel board 8, a RAM13 is provided instead of a bus controlling system and the RAM13 is controlled by a direct memory access controller (DMAC)10. Namely, the DMAC10 controls the data transfer between an I/O controlling circuit 9 and the RAM13. The DMAC10 accesses the RAM13 inside the board 8 without using a system bus 4. Therefore, the necessity of a bus controlling circuit in the I/O channel board 8 is eliminated. In addition, the bus 4 utilizing efficiency of the CPU2 is improved since the DMAC10 does not require the bus 4 for accessing a RAM7. On the other hand, the RAM13 can be accessed from th other through the bus 4, the CPU2 can easily access data in the RAM13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a DMA (direct memory access) control circuit system, and particularly to an MA control circuit system, which is preferably used for bus control in a single-board type computer system.

[Background of the invention]

A conventional DMA control circuit system will be explained with reference to FIG. As is well known, this system includes a CPU (central processing unit) board 1, a memory board 6, and an O channel board 8 connected to a system bus 4.

The CPU board 1 includes a CPU 2, a ROM (read only memory) 3 in which a control program is written,
It is composed of a bus arbiter 5 that controls the system bus 4 in a time-division manner. Here, the CPU 2 sequentially reads and executes the programs in R,0M3. The bus arbiter 5 controls the right to use the system bus 4. In other words, if you want to use the system bus 4 for a device such as CPU 2 or DMAC (
When the direct memory access controller 10 or the like issues a request to use the system bus 4 to the bus arbiter 5, the path arbiter 5 receives this request signal. Then, there is no other device issuing a request to use bus 4,
At that time, as soon as it is determined that the bus 4 is not in use, a signal is sent to the device that has made the request to allow use of the system bus 4. If another device is using the bus 4, the device is forced to wait until that device finishes using the bus 4. On the other hand, if multiple devices request the use of the system bus 4 at the same time, the path arbiter 5 performs control to allocate the right to use the system bus 4 to the requesting device according to a predetermined priority order. do.

The memory board 6 incorporates a RAM (random access memory) 7. The RAM 7 functions as a working area for the CPU 1 and also stores data and programs.

The first channel board 8 has the first control circuit 9 and the DMAC.
10, a buffer 11 for address signals and data signals, and a bus control circuit 12 for using the system bus 4. Here, the V0 control circuit 9 is a circuit for transferring data at high speed between external input/output devices connected to it, and the specific circuit is The composition is different. DMACl0 connects the 1tlea circuit 9 and RA
This is for transferring data to and from M7 without going through the control of CPU2. That is, when a request to use the system bus 4 is given to the bus arbiter 5 through the bus control circuit 12 and a use permission signal is received from the path arbiter 5, data is transferred to and from the RAM 7 via the system bus 4. It is. At this time, the transfer data and the address of the transfer destination AM7 are supplied through the buffer 11.

However, in a system with such a configuration, the CPU 2 usually mainly uses the system bus 4, but if the CPU 2 is to transfer C data through the support circuit 9, the DMAC
l0 will use system bus 4. Therefore, the CPU 2 and DMACl0 share the system bus 4 in a time-sharing manner, which has the drawback of reducing processing speed and system efficiency. Furthermore, when the system becomes larger and multiple CPUs and DMACs are used, the system efficiency tends to deteriorate further.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA control circuit system that eliminates the drawbacks of the prior art as described above and improves processing speed and processing efficiency in a single board type computer system 1.

[Summary of the invention]

The present invention relates to a CPU board equipped with a CPU, a channel board to which an external input/output device is connected, and equipped with a left memory access (DMA) control means for controlling data transfer between the input/output device and the memory. connected to at least a common bus. In other words, there is a D in this channel board.
A memory that can be controlled by the MA control means is provided, and the memory device can access this memory under the control of the DMA control means without using the common bus, and the CPU on the CPU board can also access the memory via the common bus. This memory is configured so that it can be accessed.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG. 2. In FIG. 2, the same parts as those shown in FIG. 1 are given the same numbers. Characteristics of conventional bus control circuit 12 on channel board 8
This means that the RAM 13 is newly incorporated into the channel board 8. DMAC1
0 controls data transfer between the control circuit 9 and the RAM 13. Conventionally, the DMAC 10 accessed the RAM 7 outside the board 8 through the system bus 4, which required bus control. However, in this embodiment, the DMAclQ accesses the AM 13 inside the board 8 without using the system bus 4. Therefore,
Since it is not necessary for the conventional bus control circuit in the channel board 8, the circuit configuration becomes simple and cost reduction can also be achieved. Also, since DMACl0 does not need to access RAM7 using system bus 4, DMACl0 does not need to access RAM7 using system bus 4.
U2 uses system bus 4 more efficiently, allowing CPU
This has the effect of increasing the processing speed of item 2. on the other hand,
Since the RAM 13 can be accessed from other devices via the system bus 4, the CPU 2 can easily access data in the RAM 13. In other words, from the perspective of the CPU 2, the RAM 7 and the RAM 13 can be regarded as memories of the same level.

In this manner, according to this embodiment, the CPU 2 can always exclusively use the system bus 4, so that the processing speed of the CPU 2 is not reduced. Moreover, data transfer with external devices is performed using the Cable channel board 8.
Since processing can be performed independently of the PU board 1, the processing speed and processing efficiency of the entire system are improved.

〔Effect of the invention〕

As explained above, according to the present invention, the DMA memory is configured to be included in the zero channel board, and DMA transfer can be performed without going through the system bus, without reducing the processing speed of the CPU. Moreover, DMA transfer can be performed independently of CPU processing, which has the effect of improving system efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer system including a DMA control board according to the prior art, and FIG. 2 is a block diagram of a computer system including a DMA control board according to an embodiment of the present invention. 1... CPU board, 2... CPU, 4... system bus, 5... bus arbiter, 6... memory board,
7...RAM, O...S'O channel board, 9...
- I10 control circuit, 10...DMAC, 11,. Buffer, 12... bus control circuit, 13... aAN
i.

Claims (1)

[Claims] A first board comprising a CPU, and a second board to which no input/output device is connected and comprising direct memory access (DMA) control means for controlling data transfer between the input/output device and the memory. In a system configured to be connected to at least a common bus, the second
A DMA control circuit characterized in that a memory that can be controlled by the DMA control means is provided in the fourth board, and the memory is configured to be accessible from the CPU on the fourth board via the bus. method.