JPH0468459A - Digital signal processor - Google Patents

Abstract

PURPOSE:To shorten time for an arithmetic processing as a whole by simultaneously and independently executing the transfer of a data to an internal data memory due to direct memory access (DMA) and an arithmetic processing such as accessing the internal data memory by an instructed operation. CONSTITUTION:First internal data memories 29 and 30 and second internal data memories 31 and 32 are switched by a memory select controller 28 so that one can be operated as for the instructed operation and the other can be operated as for the DMA simultaneously, independently and parallelly. Then, the first internal data memories 29 and 30, the second internal data memories 31 and 32 and an external memory 42 are connected through a data bus 33 exclusive for DMA to an external interface 40. Therefore, under the control of a DMA control part 23, the data can be transferred between the internal data memories 29-32 and the external data memory 42 independently of the main instructed operation of a digital signal processor. Thus, the processing of the digital data can be practically accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device that performs arithmetic processing on a digital signal sequence.

[Conventional technology]

FIG. 3 shows, for example, IEICE Technical Report, May 1989, lCD89-5. FIG. 1 is a block diagram showing a conventional digital signal processing processor shown in "R24B, 50ns Video Signal Processor". In the figure, 7 and 8 are dual-port internal data memories that can read and write two data at the same time. , 1 and 2 are a read address generation unit that calculates a read address, 3 is a write address generation unit that calculates a write destination address, and 4 is an internal data memory 7.8 and an external data memory 1.
8, a direct memory access (hereinafter referred to as DMA) control unit that transfers data regardless of instruction operations;
5, 6 and 9, 1o are selectors, 11 is a data bus for DMA transfer, 12.13 is a data bus for transferring read data, 15 is an arithmetic unit, 16 is an accumulator, 14 is the arithmetic unit 15 and the above. A data bus 17 transfers the output data of the accumulator 16, and an external interface circuit 17 performs data input/output with an external data memory 18.

Next, the operation will be explained. ◎ In advance, independent data series groups A, (at l i = 1-N) -*A, are stored in the external data memory 18.
=(al t ax=・a j y B.(b il
i = 1~N) -+B, = (b□, b2...b
, , ) are stored in advance, and these data series are transferred to the internal data memory 7.8, respectively. Next, for this data series, a.

Complex operations such as addition, subtraction, and squaring for b (a(@bi
) is performed by the arithmetic unit 15, and the data series of the composite operation is temporarily stored in the internal data memory 7 or 8, and then transferred to the external data memory 18. The actual operation when such an operation is repeated n times will be explained in detail using the flowchart shown in FIG.

First, data series A is generated in read address generation units 1 and 2. and B4. Step 5TI) Data series A and B4 are transferred from the external data memory 18 by DMA transfer.

is transferred to the internal data memory 7, and the data series B0 is transferred to the internal data memory 8 via the data bus 14 (step 5T2). Next, data series A and B. are outputted via the data bus 12 and the data bus 13, respectively, and processed by the arithmetic unit 15 and the accumulator 16, and the results are stored in the internal data memory 7.8 according to the address of the write address generation section 3. write to. This operation is repeated several times, and a compound operation is performed on each data a1 to a, l and b1 to b (step 5T3
). The final result is then written into the internal data memory 7.8. Next, set the write destination and start address of the external data memory 18 in the write address generation unit 3 (step 5T4), perform DMA transfer in data series units, and transfer data to the data bus 14 and external interface F! &
17 to the external data memory 18 (step 5TS).

The above operations are performed in parallel by pipeline processing, so it takes one complex operation to read out each n data series, process it, and write the data series to the external data memory 18 all at once. Assuming that the command operation is performed on the data n times, by executing the cycle of each step n times, ((k+3)N+53n
More than one cycle is required.

[Problem to be solved by the invention]

Since the conventional digital signal processing device is configured as described above, when accessing the internal data memory 7.8 and the external data memory 18 by command operation, the DMA
In image signal processing where transfer is not possible and a large amount of data must be processed at high speed, each data memory 7.8.
The transfer time from No. 18 occupies a large proportion of the data processing time, resulting in problems such as a decrease in data processing speed.

This invention was made to solve the above-mentioned problems, and by having an internal data memory and an external data memory that can be independently exclusive using DMA, data transfer can be performed regardless of operations by instructions. [Means for Solving the Problems] A digital signal processing device according to the present invention includes a read address generation unit that generates an address of read data based on the contents of a microprogram, and a write a write address generation unit that generates a data write destination address; a first internal data memory from which data is read and written according to each address of the read address generation unit and the write address generation unit; Independently of program execution,
A direct memory access control unit that transfers data according to a set address, and a second internal data memory that can be exclusively used when data is transferred between the external data memory and the external data memory by the direct memory access control unit, The internal data memory and the second internal data memory are switched by a memory select controller so that one operates simultaneously and independently in parallel for instruction operation and the other for direct memory access, and the first internal data memory and The second internal data memory and the external memory are connected to an external interface dedicated to direct memory access via a data bus dedicated to direct memory access.

[Effect]

The digital signal processing device of the present invention performs arithmetic processing such as data transfer to an internal data memory by DMA and access to the internal data memory by command operation.
This enables simultaneous and independent operations, thereby reducing data transfer time from an external data memory and overall arithmetic processing time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 20, 21 is a read address generation section, 22 is a write address generation section, 23 is a DMA control section that transfers data between the internal data memory and the external data memory, 24, 25, 26. 27 is a selector, 2
8 is a select controller that selects the above-mentioned data memory that can be exclusively used by DMA; 29, 30, 31, and 32 are the above-mentioned internal data memories; 29.30 is an internal data memory as the first internal data memory; 31.32 is an internal data memory; This is an internal data memory as a second internal data memory. 33
34 and 35 are data buses that transfer DMA transfer, 34 and 35 are data buses that transfer reading data, 36 is an arithmetic unit, 37 is an accumulator, 38 is a data bus that transfers output data, and 39 is data dedicated to instruction operations. An external interface circuit 40 performs input/output, and is a DMA external interface circuit that performs DMA-specific data input/output. 41 is an external data memory connected via the DMA external interface circuit 40, and 42 is a DMA external data memory that stores DMA-specific data.

Next, the operation will be explained.

Now, a data series group A has N elements. =(atlt
=1~N)→Al1=(al, a2°”aJyB−=
(b t I i = 1-N) → B, = (b+, b
2...bN) are stored in the external data memory 42 in advance. Under the above conditions, data series A. and B are DMA-transferred to the internal data memory 29.30 or 31.32 in units of data series, subjected to compound operations, and the results are transferred all together and stored in the external data memory 42. This processing operation will be explained according to the flowchart shown in FIG.

First, the start address and write address of the data series Ai, H□ are set in the DMA control unit 23 (step 5
TII). Next, the internal data memories 31 and 32 are transferred to DMA
After being controlled by the memory select controller 28 to be dedicated (step 5T12), data series A and B□ are respectively written into the internal memories 31 and 32 by DMA transfer (step 5T13). Here, D
The MA control unit 23 receives the next data series A2. The start address of B2 is set (step 5T14). Next, the memory select controller selects the selectors 24 to 24 so that the internal data memories 29 and 30 can be used exclusively for DMA and the internal data memories 31 and 32 can be used exclusively for command operations.
27 (step 5T15). This allows complex arithmetic processing to be performed in the internal data memory 31.3 as a command operation.
2 (step 5T16), transfer the next data series using the internal data memory 29.30 (step 5T17), and write the composite operation result to the external data memory 42. It is possible (step 5T18). Therefore, like traditional processors,
If the result of some arithmetic processing after data transfer requires processing such as data transfer, data transfer could become a bottleneck in processing time, but in this invention, the arithmetic processing and Since data transfer is performed simultaneously using two sets of internal data memories 29, 30 and 31, 32, such conventional problems can be solved.

Here, for n data series, k per data
If a cycle composite operation is performed, this series of operations will be (kN+4)n+3N+5 cycles. Also, D
Writing to the external data memory 42 and reading data by MA transfer are performed at each step (steps 5T19 and 5T19).
At T20), there are N cycles and 2N cycles.

Thus, in this invention, the internal data memory 29.30
and 31, 32 are switched and selectively used by a memory select controller 28 controlled by instructions from the processor, and the DMA controller 23 controls the DMA through the DMA-dedicated interface circuit 40.
Dedicated data can be input/output to/from the external data memory 42, and in parallel with this operation, complex arithmetic processing can be executed using instructions using other selected internal data memories 29-32. Therefore, it is possible to reduce the influence of the data transfer time with the external data memory on the original arithmetic processing time, and it is possible to perform high-speed digital signal processing, such as pattern matching processing of image data.

In addition, in the above embodiment, a double buffer configuration is adopted in which dual port type internal data memories 29.30 and 31.32 are each used, and the DMA bus 33 and DM
Although one A-external interface 4° is shown, the configuration and the number of these can be set arbitrarily.

〔Effect of the invention〕

As described above, according to the present invention, by setting the internal data memory and external data memory that can be exclusively used for DMA transfer via the DMA external interface circuit, data can be transferred independently of the main command operation of the digital signal processing processor. Since the configuration is such that data is transferred between the internal data memory and external data memory under the control of the DMA control unit, the data transfer time does not affect the processing time due to command operation, and the digital This has the effect of speeding up data processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal processing device according to an embodiment of the present invention, FIG. 2 is a flowchart showing the procedure of data transfer and arithmetic processing according to an embodiment of the invention, and FIG. 3 is a conventional FIG. 4 is a block diagram showing the configuration of the digital signal processing device, and FIG. 4 is a flowchart showing the procedure of data transfer and arithmetic processing according to FIG. 20.21 is a read address generation unit, 22 is a write address generation unit, 29.30 is a first internal data memory, 31.32 is a second internal data memory, and 23 is a direct memory access control unit (DMA control Department), 28
1 is a memory select controller, 33 is a data bus dedicated to direct memory access, 40 is an external interface, and 42 is an external data memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (2 others) Figure Figure

Claims (1)

[Claims] A read address generation section that generates an address for read data and a write address generation section that generates a write destination address for write data based on the contents of a microprogram; a first internal data memory in which data is read and written in accordance with each address; a direct memory access control unit which transfers data in accordance with set addresses independently of the execution of the microprogram; and the direct memory The second internal data memory, which can be used exclusively when data is transferred between the access control unit and the external data memory, and the first internal data memory and the second internal data memory, one for command operation and the other for command operation. a memory select controller that simultaneously switches to operate independently and in parallel for direct memory access;
A digital signal processing device comprising: an internal data memory; and an external interface dedicated to direct memory access that connects the second internal data memory and the external data memory via a data bus dedicated to direct memory access.