JPH027129A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To execute the parallel operation without being conscious of the interference between plural arithmetic units by simultaneously processing plural instructions and writing the processing result into one shared register. CONSTITUTION:First, the instruction of an address shown by a program counter is taken out from an instruction memory and the instruction memory can simultaneously take out two instructions. The read instruction is once fetched into an instruction buffer. An instruction interpreting part interprets respective instructions and prepares the instruction for an arithmetic part and a register file. The arithmetic part executes the operation to the data from the register file and stores it into the register file. Consequently, in a next instruction, the result can be used even by any arithmetic units and it is not necessary to be conscious of the interference between plural arithmetic units.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an arithmetic processing device that performs arithmetic operations based on instructions stored in a memory.

(Prior Art) Conventional processors are so-called Neumann type computers that interpret and execute instructions at -time φ here, and therefore have a limited execution speed. To avoid this, interpret and execute multiple instructions at the same time.

There were so-called parallel execution computers.

However, with these parallel computers, it is difficult to synchronize each computer or to transfer information between the computers. Additionally, in order to successfully perform a preliminary run, a special way of writing a program or a compiler was required.

(Problem to be solved by the invention) In this way, in the conventional device, control between computers is controlled by I! ! The problem with v-5 is that it is sloppy and requires a special way of writing programs.

The present invention has been made to solve this difficulty, and its purpose is to provide a computer that can execute programs in parallel without having to write a special program, thereby increasing the execution speed.

[Structure of the invention]

(Means for Solving Problem A) The present invention makes it possible to increase the speed of 4I arithmetic units by sharing one register file (
It is strained.

(1 Effect) In the present invention, by processing multiple instructions simultaneously and writing the processing results to one shared register, the next instruction can be processed. ltF, the results can be used on any computing device.
! It's straining. Therefore, there is no need to worry about interference between a plurality of arithmetic units, and arithmetic operations can be executed in parallel. By providing a mechanism to check the interoperability of the IC#, there is no need to be aware of parallelism.

(Embodiment) FIG. 1 shows an example of an arithmetic processing device according to the present invention. This example has two calculation units. first,
The instruction at the address indicated by the program color is retrieved from the instruction memory.

It is possible to take out two instructions at the same time.

In this example, it is assumed that reading is performed from consecutive addresses, so there is one program counter.

The read instruction is then taken into the instruction buffer. The instruction interpreter interprets each instruction @ and creates instructions for the arithmetic unit and register file 1. The arithmetic unit performs arithmetic operations on data from the register file and stores it in the register file.

The memory address register is a register that points to an address in the data memory to be read. 4N The data to be read is supplied from the register file, and the read data is
Stored in register file.

The operation will be explained using the following example.

FIG. 2(a) is an example of a portion of a program written in a high-level language. This program is simple, storing the Cth element of the array in a, and storing the sum of a, b, and C in e. When this is expanded into instructions, as shown in Figure 2 (To), an ordinary computer will expand into 8 instructions. Here, #b indicates the starting address of the b array. On the other hand, according to the present invention.

Even if the memory port is 1 (1!L/), by rearranging it as shown in Figure 3, parallel execution is possible.
Execution can be completed in 5 steps.

Even with such a simple example, the advantages of the present invention are obvious.

In addition, it is relatively easy to rearrange the combinations in advance using a program.
Humans don't need to be aware of it. Furthermore, by checking the hardware for interference during execution, it is possible to run the same program as on a computer with only one arithmetic unit.

For example, in the arithmetic unit shown in diagram M1, there is a means for determining the execution priority of fetched instructions, a means for detecting whether the execution result of a higher priority instruction is used as a lower instruction, and If it is used, you can add a means to delay the execution of lower priority instructions.

Furthermore, the present invention is not limited to the example shown in FIG. 1; a part of the register file may be shared, and the rest may be unique to each arithmetic device.

The number of ports written to data memory is not one, but multiple.
You can also strain it.

Further, by cascading the arithmetic units, it is possible to process long data in one tarok.

〔Effect of the invention〕

As stated above, according to the present invention, a program written in a high-level language can be written without making any changes.
Parallel execution is possible, making it possible to create a computer that can run at high speed with the same Glock frequency.

From this, the advantages of the present invention are clear.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a program written in a high-level language and an example of changing the program to a command line. FIG. 3 is a diagram showing an example in which the program program shown in FIG. 2 is replaced at the instruction level.

Claims (3)

[Claims] (1) An instruction interpretation section that interprets each of the plurality of instructions retrieved from memory, a plurality of operation sections that perform operations according to the interpretation results of each of the plurality of instructions, and a plurality of operation sections that An arithmetic processing device characterized by comprising a digital file section for writing output data and supplying data to be input to each arithmetic section. (2) The arithmetic processing device according to claim 1, wherein the plurality of instructions retrieved from the memory correspond to consecutive addresses. (3) The instruction interpretation unit detects whether or not the execution result of a high-priority instruction among multiple instructions is to be used in a low-priority instruction. Based on this detection result, the arithmetic unit selects a low-priority instruction 2. The arithmetic processing device according to claim 1, wherein execution of the arithmetic processing device is delayed.