JPH02217924A - Storing processing system for data processor - Google Patents

Abstract

PURPOSE:To improve the performance of a pipeline processing by delaying only a writing command until the determination of an operated result to be storing data in the case of using the result of a preceding operation instruction by the succeeding STORE instruction. CONSTITUTION:An operation pipeline type data processor is constituted of an instruction unit 1 for decoding an instruction, a storage unit 2 for storing instructions and data and an operation unit 3 for executing operation specified by an instruction. When the preceding instruction exists at the time of executing a STORE instruction, the STORE instruction starts to be executed prior to the completion of the processing of the preceding instruction, whether the source register of the STORE instruction coincides with the destination register of the preceding instruction or not is checked, and when both the registers coincide with each other, the memory writing command of the STORE instruction is delayed until the operated result of the preceding instruction is determined. Consequently, the performance of the pipeline processing can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a store processing method suitable for an arithmetic pipeline data processing device.

[Prior Art] Fig. 3 shows a schematic configuration of a data processing device, in which 1 is an instruction unit that decodes instructions, 2 is a storage unit that stores instructions and data, and 3 is an operation unit that executes the operation specified by the instruction. In order to improve the processing capacity of the data processing device, the calculation pipeline representing the unit divides the time required for calculation execution into multiple cycles in the calculation unit 3.
This method allocates multiple different instruction processes to each cycle and performs pipeline control on the arithmetic unit.2Here, the execution cycle of the arithmetic unit is expressed as E (Execution
n cycle), N (Normalize c
ycle), and the subsequent register storage cycle is called P (Put Away).

FIG. 2 shows the configuration of a conventional arithmetic unit. Is this configuration floating point? This is an example of an A calculation unit, 11.12 is a selector, 13, 14, 16, 17゜] 9 is a work register, 15 is a preshifter, 18 is a parallel adder, 20 is a postshifter, 21 is an operation result register, and 22 is an In the register group, 23 is a store data register, 24, 26 is a selector, 25 is a buffer register, 30 is an operand input control circuit, 31 is a memory request control circuit, and 32 is a selector control circuit.

The operation of the conventional arithmetic unit shown in FIG. 2 that is directly related to the present invention will be described below.

When a store instruction is issued, processing of this store instruction is started without waiting for the processing of the preceding instruction to finish, and at that time, the data held in the corresponding register (source register) of the general-purpose register group 22 is transferred to the store data. First, register 14 via operand bus] 02 and selector 12.
Set to .

Next, this store data is transferred from l1ll' to the next register 25 and 23 via selectors 24 and 26 at a cycle pitch.During the transfer of this store data, selector 24 selects If the destination register and the source register of the store instruction match, the operation result of the previous instruction on the line 104 is selected and set in the register 25 in place of the old store data.

Similarly, if the destination register of the preceding instruction and the source register of the store instruction match, the selector 26 selects the operation result of the preceding instruction on the signal line 104 and stores it in the register 23 instead of the old store data. Set to . The selector control circuit 32 controls these selectors 24 and 26 to ff11111.

As described above, conventionally, the preceding operation result and the data read from the source register of the instruction to be stored are set in a register, and the store instruction selects one of the values and stores it in the store data register. It was set to 23.

[Problem to be solved by the invention] By the way, conventionally, as a method for improving processing speed,
A so-called parallel processing method in which a plurality of instructions (for example, an arithmetic instruction and a store instruction) are simultaneously executed within the same cycle at one point in an arithmetic pipeline is known from Japanese Patent Application Laid-Open No. 131230/1983.

However, with the conventional technology shown in Figure 2 above, for example, when processing an arithmetic instruction and a store instruction in parallel, the arithmetic results are transferred in the same cycle, making parallel processing impossible. .

An object of the present invention is to not only make it possible to execute a subsequent store instruction without waiting for the completion of a preceding operation, but also to enable execution of a preceding operation instruction and subsequent store instruction in a data processing device that processes multiple instructions in parallel. An object of the present invention is to provide a store processing method for a data processing device that can simultaneously process store commands.

[Means for Solving the Problems] In order to achieve the above object, a store processing method of a data processing device according to the present invention provides a data processing device that adopts an arithmetic pipeline control method, in which a store instruction is executed in advance. When an instruction exists, the execution of the store instruction is started before the processing of this instruction is completed, and the source register of the store instruction and the destination register of the preceding instruction are checked to see if they match or not. When they match, the memory write instruction of the store instruction is delayed until the operation result of the preceding instruction is determined.

The present invention can also be applied to a data processing device that can process multiple instructions in parallel. In this case, the execution of an arithmetic instruction and a store instruction is started in parallel, and the It is checked whether the destination register and the destination register match, and if both registers match, the memory write instruction of the store instruction is delayed until the operation result of the preceding instruction is determined.

According to another aspect of the store processing method of a data processing device according to the present invention, when a store instruction is executed following an arithmetic instruction in a data processing device that employs an arithmetic pipeline control method, the store instruction is stored as store data. When using the operation result of an operation instruction, start execution of the store instruction before the operation result of the operation instruction is determined, and if the operation result is not determined when the original memory write instruction occurs, the operation result is The memory write timing of the store command is delayed until the time when the data can be used as store data.

A data processing device according to the present invention employs an arithmetic pipeline control method, and includes a memory control unit that generates a memory write instruction signal in response to a store instruction, and a memory control unit that generates a memory write instruction signal from the memory control unit. a delay means for delaying, a selection means for selecting one of the memory write instruction signals before and after the delay of the delay means, and a memory write instruction signal that is original when executing a store instruction that uses the operation result of the operation instruction as store data. and a selection control means for detecting a case where the calculation result is not determined at the time of occurrence and controlling the selection means in accordance with the detection result.

According to another aspect, the data processing device according to the present invention employs an arithmetic pipeline control method, and includes a memory control means that generates a memory write instruction signal in response to a store instruction, and a calculation result of the arithmetic instruction. a detection means for detecting a case where the arithmetic result is not determined at the time of generation of the original memory write instruction signal when executing a store instruction using the memory write instruction signal as store data; and a delay means for delaying by a predetermined time for each calculation instruction.

According to still another aspect, a data processing device according to the present invention employs an arithmetic pipeline control method, and includes a memory control unit that generates a memory write instruction signal in a specific cycle of a store instruction; detecting means for detecting whether or not a destination register of the arithmetic instruction and a source register of the store instruction match when there is an arithmetic instruction that started execution earlier or at the same time; When,
The write instruction signal is provided with a delay means for delaying the write instruction signal until a cycle after the calculation result of the calculation instruction is determined.

[Operation] According to each of the above means of the present invention, when the result of a preceding operation instruction is used in a subsequent store instruction, only the memory write instruction is delayed until the operation result that becomes the store data is determined, so that the store can be executed. Since there is no need to delay the start of instruction execution, the performance of pipeline processing can be improved. A store operation that delays such a write instruction is hereinafter referred to as "default door processing."

This day-first door processing is particularly effective in data processing devices that process multiple instructions in parallel.When processing arithmetic instructions and store instructions in parallel, only memory write instructions are By delaying the instruction until it is finalized, it becomes possible to process the arithmetic instruction and the store instruction in parallel.

[Embodiment] An embodiment of the present invention in which a memory request signal as a memory write instruction can be delayed by one cycle will be described below with reference to FIG.

FIG. 1 is a block diagram of one embodiment of an arithmetic unit according to the present invention. In this figure, the same components as in FIG. 2 are given the same reference numerals.

In this embodiment, the selector 24 and register 2 in FIG.
5 is deleted, and the selector # control circuit 32 is replaced with a simplified selector control circuit 35. The selector control circuit 35 recognizes the case where the destination register of the preceding operation instruction and the source register of the subsequent store instruction match, and the operation result of the preceding operation instruction is not in time for the subsequent store instruction, and takes appropriate action. Generates selector control signals. On the other hand, a 1-bit memory request register 33 for the purpose of delaying a memory write instruction by one cycle and a selector 34 for selecting either the input or output of this register 33 are added.

The operation of the arithmetic unit shown in FIG. 1 will be explained below.

First, the operation result of the preceding operation instruction is determined without delay, the subsequent store instruction is executed without waiting, and the destination register of the preceding instruction and the source register of the store instruction match. Consider the case. In this case, the operation result of the preceding instruction is stored in the register 21.
Since it has been determined, this is transferred to the selector 12 via the line 104', and this store data is transferred to the register 23.

When the memory request control circuit 31 issues a memory request, store data is written to the storage unit via the signal line 105. At this time, the memory request issued from the memory request control circuit 31 is sent to the selector 3.
4 and sent to the storage unit via signal line 110.

Next, consider a case where the operation result of the preceding operation instruction does not arrive in time for the subsequent store instruction. In this case, execution of the subsequent store instruction is started, but since the output signal line 109 of the register 33 is selected by the selector 34, the memory request is not immediately sent to the storage unit, but the memory request is sent via the signal line 108'. The memory request is delayed by one cycle by the register 33 and sent to the storage unit at the timing when the operation result is obtained in the store data register 23 via the selector 26.

In this way, according to the present embodiment, compared to the conventional device shown in FIG. 2, with less hardware and simpler control,
As in the prior art, in the arithmetic pipeline control method, a subsequent store instruction can be started without waiting for the arithmetic result of the preceding arithmetic instruction to be determined.

Next, an example of operation when a plurality of instructions are processed in parallel will be described.

FIG. 4(a) shows a case in which a preceding add instruction AE and a subsequent store instruction STE are processed in parallel.

AE all instruction destination register number and STET
In Figure 0, which shows a time chart when the default door processing is executed when the E10-S register numbers match, the upper row of each cycle indicates the preceding instruction, and the lower row indicates the subsequent instruction.

It is also assumed that the AE all-instruction operation results are obtained in the N stage, and the STETE10 memory request from the memory request control circuit 31 is sent out in the N stage when the store data is set in the store data register 23 (FIG. 1).

When the ΔE instruction and STETE are processed in 10 columns, the operation results of all AE instructions are obtained in the second cycle.

It is set in the store data register 23 (Fig. 1) in the third cycle, and the STETE10 memory request is sent in the second cycle, but it is delayed to the third cycle by the deferential door processing mentioned above, and the store data register is set at the same time. Send it to memory along with the data.

Here, since the execution of the AE/STE instruction to be processed in parallel is completed in the E stage, the instruction following the AE/STE instruction can be executed in the second cycle, and processing performance can be improved.

On the other hand, as shown in FIG. 4(b), if the default door processing is not performed as in the past, even if the data processing device is capable of parallel processing, the STETE10
The memory request must wait until the operation results of all AE instructions are finalized. Therefore, the instruction following the AE/STE instruction cannot be started until the third cycle, which is one cycle later than in Figure 4 (8). , the parallel processing function cannot be used effectively.

In the above embodiment, the configuration is shown in which the memory request is delayed by one cycle, but depending on the type of operation instruction,
Another embodiment that can deal with the case where the determination of the calculation result is further delayed is shown in FIG. 5, in which the same components as in FIG. 1 are given the same reference numerals.

The difference in the embodiment shown in FIG. 5 from that shown in FIG. 1 is that the register 33 is composed of three stages of 1-bit registers 33-1 to 33-3, and the output is delayed by one cycle of the xth order. and the selector 34 outputs the outputs 108-1-108- of each stage according to the output of the selector control circuit 31.
3 and the output 108 of the memory request control circuit 31. Selector control circuit 3
1 not only detects a match between the destination register of the preceding operation instruction and the source register of the subsequent store instruction, but also recognizes the definite cycle of the operation result for each type of preceding operation instruction and outputs the selection control signal of the selector 34. occurs. The control of the selector 26 is performed according to the determination of the calculation result.
The calculation result is stored in the register 23 and executed so as to be used as store data. According to this embodiment, the memory write instruction can be delayed up to three cycles depending on the type of arithmetic instruction. If further delay is required.

The number of stages of the register 33 may be increased.

In each of the above embodiments, a case has been described in which the present invention is applied to floating point arithmetic instructions, but the present invention is not limited to this.

[Effects of the Invention] According to the present invention, when the result of a preceding operation is used in a subsequent store, by using a 'default door',
With less hardware and simpler control than before, it is possible to start processing a store instruction without waiting for the completion of the preceding instruction in arithmetic pipeline control, especially when multiple instructions are executed in parallel. This is effective in the data processing device that processes the data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the arithmetic unit of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a conventional arithmetic unit, FIG. 3 is an overall configuration diagram of a data processing device, and FIG. 4 is a block diagram showing an example of the configuration of a conventional arithmetic unit. A timing diagram illustrating the arithmetic pipeline of the present invention,
FIG. 5 is a block diagram of another embodiment of the invention. 11.12,24,26.34...Selector, 13°14.16,17,19,21.23...Register. 15, 20... Shifter, 18... Parallel adder, 22
...Register group, 33...1 bit register, 34
... Selector, 35... Selector control circuit.

Claims (1)

[Claims] 1. In a data processing device that employs an arithmetic pipeline control method, when a store instruction is executed and a preceding instruction exists, the execution of the store instruction is started before the processing of the instruction is completed. At the same time, it is checked whether the source register of the store instruction and the destination register of the preceding operation instruction match, and if both registers match, the above store is executed until the operation result of the preceding instruction is determined. A store processing method for a data processing device characterized by delaying a memory write instruction of an instruction. 2. In a data processing device capable of processing multiple instructions in parallel, execution of an arithmetic instruction and a store instruction is started in parallel at the same time, and the source register of the store instruction and the destination register of the arithmetic instruction match. A store method for a data processing device, characterized in that it is checked whether the registers match, and when the registers match, the memory write instruction of the store instruction is delayed until the operation result of the preceding instruction is determined. 3. In a data processing device that employs an arithmetic pipeline control method, when a store instruction is executed following an arithmetic instruction, if the store instruction uses the arithmetic result of the arithmetic instruction as store data, the arithmetic operation of the arithmetic instruction In addition to starting execution of the store instruction before the result is determined, if the operation result is not determined when the original memory write instruction occurs, the memory write timing of the store instruction is changed until the point where the operation result can be used as store data. A store processing method for a data processing device characterized by delaying the . 4. A data processing device employing an arithmetic pipeline control method, comprising: memory control means for generating a memory write instruction signal in response to a store instruction; delay means for delaying the memory write instruction signal from the memory control means; a selection means for selecting either the memory write instruction signal before or after the delay of the delay means; and a selection means for selecting either the memory write instruction signal before or after the delay of the delay means; 1. A data processing device comprising: selection control means for detecting a case in which the selection means is not determined, and controlling the selection means according to the detection result. 5. In a data processing device that employs an arithmetic pipeline control method, a memory control means that generates a memory write instruction signal in response to a store instruction, and a memory control means that generates a memory write instruction signal in response to a store instruction, and a a detection means for detecting a case where the operation result is not determined at the time when the memory write instruction signal is generated; 1. A data processing device comprising: delay means for delaying the data by the amount of time. 6. In a data processing device that employs an arithmetic pipeline control method, there is a memory control means that generates a memory write instruction signal in a specific cycle of a store instruction, and an arithmetic instruction that starts execution before or at the same time as the store instruction. a detection means for detecting whether or not a destination register of the arithmetic instruction and a source register of the store instruction match; 1. A data processing device comprising: delay means for delaying until a cycle after a calculation result is determined.