JPH0342721A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the queuing time for a pipe line processing by bypassing an instruction buffer to transfer processing data in a unit length when a part of processing data concerned of the unit length required for deocding is not transferred to the instruction buffer. CONSTITUTION:A memory control unit 4 outputs an effective signal 7 to a decision selection means 8 whenever a unit instruction bit string is written in the instruction buffer 2 from a first transfer means 5. The decision selection means 8 holds storage information showing to which register in the first transfer means 5 or the instruction buffer 2 respective unit instruction bit strings are stored based on the effective signal 7. In a normal case, the unit instruction bit strings are transmitted to a second transfer means 6 through the instruction buffer 2, and are decoded in an instruction decoder 3. When the unit instruction bit string to be decoded is not stored in the instruction buffer 2, the strings are transferred to the second transfer means 6 through bypass transfer circuits P1-P4 from the first transfer means 5 by the command of the decision selection means 8.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an information processing device that processes digital data, and in particular to a microprocessor that performs pipeline processing using variable-length instructions, and which reduces the waiting state of pipeline processing. , the purpose of which is to provide an information processing device that improves processing speed, and includes: an instruction buffer that temporarily stores a plurality of unit-length processing data; an instruction decoder that simultaneously decodes the n unit-length processing data; a memory management unit that controls the transfer of processing data; a first transfer unit that temporarily stores the n pieces of unit processing data transferred from the memory management unit and transfers it to the instruction buffer; In the information processing apparatus, the information processing apparatus includes a second transfer means for temporarily storing the n pieces of transferred unit length processing data and transferring it to the instruction decoder; The present invention includes bypass transfer means capable of transferring the specific processing data to the second transfer means without passing through the instruction buffer when the processing data has not yet been transferred to the instruction buffer.

[Industrial application field]

The present invention relates to an information processing device that processes digital data, and particularly to a microprocessor that performs pipeline processing using variable-length instructions.

Pipeline processing and instruction briefetch are generally used as techniques for speeding up processing in microprocessors.

Pipeline processing is a method that speeds up the processing using hardware when similar processing is repeated by starting the next operation before one operation finishes and executing multiple operations while overlapping. be. Instruction briftetch is a so-called prefetching technique that reads in advance the instruction to be processed next.

In a microprocessor that performs pipeline processing and instruction briefetch in parallel, pipeline processing is fast, but due to the delay in instruction briefetch and the accompanying delay in transferring instructions to the instruction decoder, pipeline processing is put into a standby state, which slows down the overall process. However, the problem is that the instruction processing speed is not improved. Therefore, it is necessary to efficiently perform instruction briefetch and instruction transfer to the instruction decoder so as to reduce the waiting state of pipeline processing as much as possible.

[Conventional technology]

FIG. 3 shows a block diagram of a conventional microprocessor. Here, it is assumed that the processing of the instruction decoder is performed for every four unit instruction bit strings.

The microprocessor 1 includes an instruction buffer 2 having m registers R1 to Ro for temporarily storing a unit instruction bit string group, an instruction decoder 3 that simultaneously decodes the unit instruction bit string group, and a unit instruction buffer 2 in a memory (not shown). A memory management unit 4 that controls bit string transfer processing; a first transfer means 5 that temporarily stores a plurality of unit instruction bit strings transferred from the memory management unit 4 and transfers them to the instruction buffer 2; A second transfer means 6 for simultaneously transferring unit instruction bit string groups to the decoder 3 is provided.

The general operation is as follows. The unit instruction bit string is sequentially transferred from the memory management unit 4 to the first transfer means 5. The first transfer means 5 temporarily stores these unit instruction bit string groups, and sequentially writes them into the instruction buffer 2 in response to a write instruction signal (not shown) from the memory management unit 4.

Further, the unit instruction bit string written in the instruction buffer 2 is transferred to the second transfer circuit 6. In the second transfer circuit 6, when the unit instruction bit string group is stored, the instruction decoder 3
and decodes the instructions.

FIG. 4 shows an explanatory diagram of an instruction processing execution cycle.

Here, A, B, C, DSE, F, G, and H each indicate a unit instruction bit string, and processing is performed in this order. Further, X indicates that there is no unit instruction bit string.

In the first instruction decode stage DC1, since the unit instruction bit string group (A, B, C, D) has already been taken into the second transfer means, the unit instruction bit string group (A, B, C, D) is transferred from the second transfer means 6 to the instruction decoder 3. A, B, C, D) are output and decoded.

Here, since this microprocessor handles variable length instructions, the unit instruction bi-soto sequences C and D
When it is determined that the unit instruction bit strings C and D belong to a different instruction from the unit instruction bit strings A and B, the unit instruction bit strings C and D are transferred from the instruction buffer 2 to the second transfer means 6 again. At this time, since the instruction is decoded for every four unit instruction bit strings, the unit instruction bit strings E and F, which should be decoded at the same time as the unit instruction bit strings C and D, must be transferred to the second transfer means 6. . However, since the unit instruction bit strings E and F are stored in the first transfer means and have not yet been transferred to the instruction buffer 2, the second transfer means cannot take them in. Therefore, the processing data consists only of the unit instruction bit strings C and D, which cannot be processed and become invalid data. Therefore, the second decode stage DC2 is in a standby state (WAIT), and subsequent pipeline processing is also in a standby state.

As described above, unless a sufficient number of valid instruction bit strings are prepared in the instruction buffer 2, the instruction will not be transferred to the instruction decoder 3. That is, unless a unit instruction bit string group is prepared, the instruction is not transferred to the instruction decoder 3. Also, if sufficient preparation is not done, invalid data, such as (C, D.

X, X) were transferred as-is as completely invalid data.

[Problem to be solved by the invention]

In the above conventional example, normally the unit instruction bit string is not transferred to the instruction decoder until four unit instruction bit strings are stored in the instruction buffer, and even if it is transferred, it is not completely transferred. Since the data is transferred as invalid data, there is a problem in that a waiting state occurs in pipeline processing.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an information processing apparatus that reduces the waiting state of pipeline processing and improves processing speed.

[Means to solve the problem]

In view of the above problems, the present invention provides an instruction buffer (2) that temporarily stores a plurality of unit-length processing data, and an instruction decoder (3) that simultaneously decodes the n unit-length processing data.
), a memory management unit (4) that controls the transfer of the processing data, and a memory management unit (4) that temporarily stores the n unit-length processing data transferred from the memory management unit (4), and the instruction buffer (2). ), and a first transfer means (5) for transferring n to the instruction buffer (2);
a second transfer means (6) for temporarily storing the unit length processing data and transferring it to the instruction decoder (3);
In the information processing apparatus, when the specific unit-length processing data in the ↓-th transfer means (5) has not yet been transferred to the instruction buffer (2), the specific unit-length processing data can be transferred to the second transfer means (6) without going through the instruction buffer (2).
[Operation] According to the present invention, when a part of the unit-length processing data necessary for decoding has not yet been transferred from the first transfer means to the instruction buffer, the bypass transfer means transfers the unit-length processing data to the first transfer means. The command is directly transferred to the second transfer means without going through an instruction buffer.

〔Example〕

Embodiments of the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 shows a block diagram of an information processing device. Components that are the same as those in the conventional example shown in FIG. 3 are designated by the same reference numerals, and detailed explanations will be omitted.

The difference from the conventional example shown in FIG. determination selection means 8 for holding storage information as to where the unit instruction bit string is stored and for determining whether or not to perform bypass transfer of a unit instruction bit string and selecting and executing bypass transfer or normal transfer; and for performing bypass transfer. bypass transfer circuits P1 to P4.

The memory management unit 4 outputs a valid signal 7 to the determination selection means 8 every time a unit instruction bit string is written from the first transfer means 5 to the instruction buffer 2.

Based on the valid signal 7, the determination selection means 8 holds storage information indicating whether each unit instruction bit string is stored in any one of the registers in the ↓-th transfer means 5 or the instruction buffer 2.

The operation will now be described with reference to the explanatory diagram of the instruction processing execution cycle in FIG. In the figure, A and B.

CSD, E, F, G, and H each indicate a unit instruction bit string, and processing is performed in this order.

In the first instruction decode stage DCI, the unit instruction bit string group (A, B, C, D) has already been transferred to the second transfer means 4.
Therefore, the unit instruction bit string group (A, B, C, D) is output from the second transfer means 4 to the instruction decoder 3 and decoded. As a result of decoding, when it is determined that the unit instruction bit strings C and D belong to a different instruction from the unit instruction bit strings A and B, the unit instruction bit strings C and D are transferred from the instruction buffer to the second transfer means 6 again. be transferred. At this time, since instruction decoding is performed for every four unit instruction bit strings, unit instruction bit strings E and F to be decoded must be transferred at the same time as unit instruction bit strings C and D. However, the determination and selection means 8 reveals that the unit instruction bit strings E and F are still held in the first transfer means 5 and have not been transferred to the instruction buffer 2. Based on this, the determination selection means 8 performs bypass transfer of the unit instruction bit strings E and F. Then,
The unit instruction bit strings E and F are directly transferred from the first transfer means 5 to the second transfer means 6 via the bypass transfer circuits P1 and P2. Thereafter, the unit instruction bit string group (C, D, E, F) is transferred from the second transfer means 6 to the instruction decoder 3 and decoded.

As described above, even if the unit instruction bit string to be decoded is not yet stored in the instruction buffer, the first
Since the unit instruction bit string is transferred from the transfer means 5 to the second transfer means 6 via the bypass transfer circuits P1 to P4,
The second transfer means 6 can immediately transfer the unit instruction bit string group including the unit instruction bit string to the instruction decoder 3.

2 This means a reduction in the waiting time of pipeline processing.

〔Effect of the invention〕

Since the present invention is configured as described above, even if a part of the unit length processing data necessary for decoding has not yet been transferred from the first transfer means to the instruction buffer, the bypass transfer means can transfer the unit length processing data to the instruction buffer. Since unit length processing data can be transferred from the first transfer means to the second transfer means without going through an instruction buffer, the waiting time of pipeline processing can be reduced. Therefore, it is possible to improve the processing speed of the information processing device.

[Brief explanation of drawings]

Fig. 2 is an explanatory diagram of an instruction processing execution cycle in the invention; Fig. 3 is a block diagram of a conventional microprocessor; Fig. 4 is a conventional instruction processing diagram. It is an explanatory diagram of an execution cycle. ■...Microprocessor 2...Instruction buffer 3...Instruction decoder 4...Memory management unit 5...↓th transfer means 6...Second transfer means 7...Valid signal 8... - Judgment selection means P1 to P4...Bypass transfer circuits R1 to Rm...Registers

Claims (1)

[Scope of Claims] An instruction buffer (2) that temporarily stores a plurality of unit-length processing data, an instruction decoder (3) that simultaneously decodes the n unit-length processing data, and transfer control of the processing data. a memory management unit (4) that temporarily stores the n unit-length processing data transferred from the memory management unit (4) and also stores the instruction buffer (
2), and a second transfer means (5) for temporarily storing the n unit length processing data transferred from the instruction buffer (2) and transferring it to the instruction decoder (3). In an information processing apparatus comprising a transfer means (6), when the specific unit length processing data in the first transfer means (5) has not yet been transferred to the instruction buffer (2), An information processing apparatus comprising bypass transfer means (8, P_1 to P_4) capable of transferring unit-length processing data to the second transfer means (6) without passing through the instruction buffer (2).