JPS6259829B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction processing synchronization control method when processing is interrupted due to memory busy or the like in vector processing.

Second operand A= with multiple elements
The third operand B has a plurality of elements, a ₀ , a ₁ , ......, a _o-1 = b ₀ , b ₁ , ......b _o-1 , and the corresponding elements are operated on, and the result is First operand, C = c ₀ , c ₁ , ......c _o-1 (Here, if the operation is addition, c _i = a _i + b _i , i is 0, 1,
There is a processing device that obtains any one of 2, . . . n-1). This is called a vector processing unit.
In contrast, the operand element is one (n
A conventional general-purpose processing device limited to 1) is called a scalar processing device. FIG. 1 shows the configuration of a vector processing device. As shown in this figure, the vector processing device includes an instruction control section, a memory access processing section that performs load and store processing for the control device MC _u of the main memory MS _u , and an arithmetic processing section including vector registers, adders, and multipliers. Be prepared. The vector register is
Accommodates multiple vector data consisting of multiple elements to be loaded/stored. A vector instruction consists of an instruction code, a first operand specification, a second operand specification, and a third operand specification. For example, VM1, 2, and 3 are multiplication instructions for multiplying the contents of vector register 2 and vector register 3 (VM: vector multi) and putting the result in vector register 1. VA4, 5, and 1 are vector addition instructions to add the contents of vector register 5 and vector register 1 (VA: vector add) and put the result into vector register 4.

When processing vector instructions, in order to perform the processing at high speed, the arithmetic processing unit has a pipeline structure, and the subsequent element is input before the arithmetic processing of the preceding element is completed.
For example, when performing a vector addition instruction, read data (READ), compare the exponents of both operands (COMPARE), shift to match the exponents (PRE SHIFT), add (ADD), and shift for normalization after operation ( It is a 6-step process: POST SHIFT), data writing (WRITE),
These are executed sequentially and simultaneously as shown in FIG. That is, for element 0, reading of a ₀ and b ₀ , index comparison, preshift, etc. are performed sequentially, and the same is true for element 1, but the timing is delayed by one processing timing τ ₀ , and the same is true for element 2. However, the timing is delayed by two processing timings, and the same applies hereafter. Therefore, the processing status of the entire element is represented by a parallelogram as shown. E0T, E1T... indicate processing of element 0, processing of element 1, etc.

By the way, in arithmetic processing, the result of a certain process TR ₁ may be used to perform the next process TR ₂ , but if the execution of the processing unit TR ₁ is delayed due to memory busy etc., the next process TR ₂ will naturally not be able to be executed. Waiting for TR ₁ processing. After the processing of TR ₁ is completed, execution of the next processing TR ₂ is started. For example, consider the following set of instructions. VL2, A (load the contents of memory address A into vector register 2), VA3, 0,
2 (Add the contents of vector registers 2 and 0 and put it in register 3), VA4, 1, 2, VL5,
B (load the contents of memory address B into vector register 5), VM6, 3, 5 (multiply the contents of vector registers 3 and 5 and put the result in vector register 6), VM7, 4, 5, this In a sequence of instructions, a process, etc. cannot be executed until the execution of the process has finished. In this way, when the result of a preceding instruction is used in a subsequent instruction, there is said to be a chain between those instructions. Since memory is used not only by the access processing unit but also by channels and others, it is not always possible to access the memory.

If there is no delay in memory access, the execution of the above instruction sequence will be as shown in FIG. That is, the instruction VL2, A is executed sequentially for each vector element E ₀ , E ₁ . As ... is written, it can be executed from the 0th, 1st, etc. elements, so if there is a delay of more than one timing from the time when the first element E0 is written to register 2, it will be executed immediately from the 0th element side. Begins. This is called chaining of vector processing. Since the next instruction only uses the result of , it may be started at the same time, but since it is the same vector added VA, it will wait for processing because it uses the same hardware. Since the result of the next instruction is only used by the instruction, it is sufficient to finish by then (storing the 0th element to register 5), and the execution is executed at an appropriate timing as shown in the figure. The instruction may be executed at the same time as the instruction if the multiplier is separate from the adder, etc., but in this example the same hardware is used, so it is executed later. Since the command uses the results of the command, it can be executed at any time after the execution of the command, but for the same reason, it is performed after the command.

In vector processing, main memory is divided into multiple banks and interleaved. However, even with interleaving, if a subsequent access comes to the same bank during the cycle time of the main memory, the subsequent access will have to wait. Furthermore, if a memory access bank competes with another device such as a channel processor (CHP), memory access for vector instructions is forced to wait. If memory access is required, chaining cannot be performed simply. For example, after the storage in register 2 up to element Ei, which is instruction processing, is completed, the next element E _i+1
Now, if memory access is made to wait,
In the instruction, elements after E _i+1 are added with meaningless data in register 2 corresponding to E _i+1 and after. Therefore, in the past, (i) when issuing a load instruction, it was confirmed that there was no bank conflict during the cycle time between each element in that instruction, and (ii) it was confirmed that there was no access from other sources such as CHP. and (iii) when the load instruction is accessing memory, chaining should be performed only when other memory accesses are prohibited, that is, there is no delay in memory access. was. Therefore, if there is a bank conflict during the cycle time in an element with the instruction, chaining cannot be performed, resulting in an instruction processing time chart as shown in FIG.

As is clear from Figure 4, with this method,
Even though some elements of the subsequent instruction can be executed, the execution of the instruction is delayed until the execution of the instruction is completed, resulting in system resources not being used effectively. Also, other devices such as CHP are forced to wait completely, reducing the effect of interleaving.

The present invention aims to improve this problem, reduce processing waiting time as much as possible, shorten the required time, and effectively utilize resources. In the present invention, chaining control is performed so that even if memory access is interrupted, elements that have been loaded so far are processed immediately.

In other words, as shown in FIG. 5, when element data is written to the vector register 2 by a load instruction, chaining is performed and the subsequent instruction is executed, but since the preceding load instruction cannot access memory, the element data is written in the middle. When it becomes impossible to load the commands, the chaining subsequent commands are stopped. At this time, if you do not check whether there is chaining or not, but simply stop the arithmetic processing that is currently running because element data could not be written to the vector register in a load instruction, synchronization control of chaining is easy. However, as in the instruction shown in FIG. 5, by interrupting the execution of the instruction, non-chaining instructions are also interrupted, resulting in poor performance.

The present invention checks whether or not a subsequent instruction is chained to a preceding load instruction, and only when chaining occurs and the writing of element data to the vector register in the preceding load instruction is interrupted, the period of the chaining is determined. During the process, the processing of subsequent chained instructions is interrupted to perform synchronous processing, and when not chained, those load instructions and other instructions are processed asynchronously in parallel, thereby making effective use of system resources. It measures performance improvement.

FIG. 6 shows a time chart in the case of the present invention. Assuming that the instruction can access up to the 4th element E ₃ and is on standby after that, there is a chaining instruction, so the element
Stop the clock when _E3 is written to register 2. Therefore, in the instruction, the processing is interrupted after only a portion of the processing of the first, second, and third elements E ₀ , E ₁ , and E ₂ has been executed. In this example, access becomes possible after four clock cycles, and instruction execution resumes when the subsequent elements E ₄ , E ₅ , . . . begin to be written to register 2. Next, an interruption occurred in the load instruction, but since there is no chaining with the arithmetic instructions being executed at the same time, the clock is not stopped, the instruction execution is interrupted, and the instruction processing is continued. In this way, in the system of FIG. 4, it took 42 clock cycles to start execution of the instruction, even though the interruption takes 4+4=8 clock cycles, whereas in the system of FIG. 6, it only takes 30 clock cycles.

In addition, this method eliminates the need for the controls in (i), (ii), and (iii) above, so when issuing a load instruction, it is checked whether or not there is a bank conflict during the cycle time between each element in that instruction. There is no need to check
Furthermore, the memory can be accessed in parallel from other devices such as CHP.

This allows even if a vector processing device has multiple memory access processing units, that is, multiple load processing units and store processing units, to perform chaining while executing them in parallel.
This is particularly effective when two load processing units are provided and each load processing unit loads the third and second operands of a subsequent arithmetic instruction while executing the subsequent arithmetic instruction in a chained manner. In addition, by changing the program order of instructions, VL instruction execution can be started earlier, so even if the processing of the VL instruction is delayed, VA instruction processing can be executed asynchronously and in parallel. , it is possible to ensure that the data is aligned in the vector register when the VM instruction is executed. In other words, delays caused by memory access can be made invisible. FIG. 7 shows an embodiment of the present invention. 10, 12, 14, 16, 1
8 is a register, 20 is an instruction decoder, 22 is an instruction transmission control circuit, 24 and 26 are matching circuits, 28 is an OR gate, 30 and 32 are AND gates, and 34 is an inverter. A rectangular frame 36 indicates an access instruction management section being executed, and a reference numeral 38 indicates an execution instruction management section.
7 corresponds to the vector processing section shown in FIG. 1, and the instruction processing section, load processing section, vector register, and arithmetic processing section correspond to those shown in FIG.

In the instruction control section, the fetched F instruction is stored in a register 10, then transferred to an instruction decode D register 12, decoded by a decoder 20, and then stored in an instruction transmission waiting Q register 14. For instructions in the register 14, check that there is no register interference between the preceding instruction and the operand register, that the arithmetic processing section is empty, and that the management sections 36 and 38 of the instruction control section are empty. Move to command execution. The above instruction sequence ~ is as follows. The fetched instruction passes through registers 10 and 12, decoder 20, register 14, and circuit 22 and enters register 16 of management section 36. The instruction is then fetched and shifted etc. into register 14 where it is transferred to circuit 22.
The command issuing conditions are checked. Since the third operand of the instruction matches the first operand of the instruction, chaining is known, and the instruction is made to wait in register 14. When the execution of the instruction progresses and the writing of the load data element to the vector register 2 starts, a flag WF indicating this is sent from the load processing section, and this is inverted by the inverter 34, so that the H (high) level signal becomes L (low). ) level signal, closes the AND gate 30, and eliminates the command transmission wait signal (L
level). Thereupon, the standby state is canceled, and the information passes through the arithmetic instruction circuit 22 to become activation information Sb for the arithmetic processing unit/access processing unit of the vector processing device, starting execution of the instruction, and is stored in the register 18 of the management unit 38. At this time, the AND gate 32 outputs a synchronous operation start signal Sc, which is input to the synchronous control circuit of the load processing section.
As a result, the load processing section stops the clock and also interrupts the execution of instruction (2) when an access interruption occurs during execution of the instruction and it becomes impossible to write a subsequent data element to the register. Se is a synchronization control signal input to the arithmetic processing unit, which stops the arithmetic operation,
Instruct restart.

The first operand of the instruction in the register 16, register number 2 in this example, is input to one terminal of the matching circuits 24, 26, and the second operand of the instruction in the register 14 is also input to the other terminal of the matching circuit 24, 26.
The third operand of the instruction in the register 14 is input to the other terminal of the register 14 (these may be reversed), and the two are compared. Therefore, if either the second or third operand of the instruction is the same as the first operand of the instruction, if the instruction is chained with the instruction, there will be a match output from either of the match circuits 24 or 26, and this will result in a match output. and gate 30,
This is one input of 32. Therefore, if there is no chaining, there is no output Sa from the AND gate 30, and the circuit 22 can immediately issue the operation instruction following the load instruction. If you are chaining,
Wait for the arrival of flag WF as mentioned above. Also, if AND32 is chaining, or gate 28
When the circuit 22 outputs the arithmetic processing unit activation signal Sd, it outputs the above-mentioned signal Sc.

F, D, Q in the lower time chart of Figure 6.
L, E, WF correspond to those explained in Fig. 7,
The instruction execution situation shown in the upper part of FIG. 6 will be explained, including instruction fetching, decoding, etc.

As explained above, according to the present invention, even if access interruption occurs, vector processing delay can be shortened as much as possible, and of course there is no problem with vector processing.
You get the benefits without any problems. In the above, we have explained synchronization control when there is chaining between the load instruction and the operation instruction, and when there is no chaining.
The present invention is not limited to this, but can be applied to cases where there is or is not chaining between the first type of instruction and the second type of instruction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the vector processing device, FIG. 2 is a diagram explaining the vector processing procedure, FIGS. 3 to 5 are diagrams explaining the instruction sequence execution status, and FIG. 6 is the control of the present invention. An explanatory diagram of the system, and FIG. 7 is a block diagram showing an embodiment of the present invention. In the drawing, the block "load processing section" is the first processing section, the block "store processing section" is the second processing section,
14, 16, 24, and 26 are chain detection means.

Claims (1)

[Claims] 1. Comprising first and second processing units that can be executed in parallel,
In an instruction processing synchronization control method in a vector processing device that processes multiple element data with one vector instruction, there is A means for detecting whether or not there is a chain is provided, and when it is detected that there is a chain and the execution of the preceding instruction is interrupted halfway through the number of element data to be processed by the instruction, the method is implemented accordingly. The execution of the subsequent outgoing instruction is interrupted until the number of element data is less than the number of element data processed by the preceding instruction, and when it is detected that there is no chain, the execution of the subsequent outgoing instruction is asynchronous with the preceding instruction. An instruction processing synchronous control method characterized by execution. 2 The first processing unit is a load processing unit, the second processing unit is an arithmetic processing unit, and the first instruction is a load instruction,
2. The instruction processing synchronization control system according to claim 1, wherein the second instruction is an arithmetic instruction.