JPH04138582A - Single instruction type parallel computer - Google Patents

Abstract

PURPOSE:To attain the rapid processing of plural instructions by providing this single instruction type parallel computer with a selection means for selecting either one of a common instruction and a local instruction stored in an instruction storing means, a selection control means for controlling the selecting operation of the selection means and a means for executing the selected instruction. CONSTITUTION:An instruction INS applied from a control circuit through an instruction bus 12 is applied to one terminal of a selector 26 to be the selection means. An instruction INSP stored in an instruction register 27 to be an instruction storing means is applied to the other terminal of the selector 26. In each arithmetic unit 2, whether the common instruction INS applied from the control circuit is to be executed or the local instruction INSP stored in the register 27 is to be executed is selected by the selector 26 in accordance with a control signal CRT applied from the control circuit and the state of an operation permission flag 24 and the selected instruction is executed. Consequently, the parallel computer can simultaneously execute plural instructions while holding the feature of a single instruction type computer and excellent effects such as the shortening of a processing time can be displayed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a single-instruction type parallel computer that executes a single instruction in parallel using a plurality of arithmetic units, and in particular, a single-instruction type parallel computer that has a local instruction register in the arithmetic unit. Concerning single-instruction parallel computers.

[Conventional technology]

Single-instruction parallel computers are used in devices that process large amounts of data by repeating simple operations, such as image processing devices.
Parallel processing enables high-speed calculation of large amounts of data. A single-instruction parallel computer has a simpler configuration and is cheaper than a multiple-instruction parallel computer.

FIG. 2 is a block diagram showing an example of the configuration of a conventional single-instruction type parallel computer.

This single-instruction type parallel computer can control the operation of each arithmetic unit using an operation permission flag, which will be described later.

In the figure, 1 is a control circuit that controls the entire parallel computer, and the control circuit 1 generates a control signal CTR, an instruction INS, and an address ADD.
2... control line 11, command bus 12, address bus 1
3, the control signal CTR generated through the same command INS
and give the same address ADD.

FIG. 3 is a block diagram showing the configuration of the arithmetic unit 2 of a conventional single-instruction type parallel computer. Control circuit 1 to command bus 1
The instruction INS sent via 2 is given to the arithmetic unit 22.

The arithmetic unit 22 is configured to selectively execute a plurality of arithmetic operations such as addition and subtraction, and performs arithmetic operations in accordance with a given instruction INS.

Address ADD given from control circuit 1 via address bus 13 is stored in local memory 23 or register group 21.
given to. The local memory 23 stores data such as calculation data and calculation results used by the calculation unit 22, and the register group 21 temporarily stores calculation data stored in the local memory 23 and data in the middle of calculation.
It is given to the arithmetic unit 22. The register group 21 also includes an operation permission flag 2 that allows the arithmetic unit 2 to operate depending on its state.
It has an area for storing 4. The state of this operation permission flag 24 is controlled by a control signal CTH applied via a control line 11 of the control circuit 1.

A conventional single-instruction parallel computer configured in this way is
At the same time, all the arithmetic units 2, 2, . . . refer to the same address ADD of the local memory 23 and perform arithmetic operations based on the same instruction INS.

Further, depending on the state of the operation permission flag 24, the operation of each arithmetic device 2 can be controlled. That is, by setting the operation permission flag to a state in which the operation is not permitted, execution of a certain instruction can be skipped for each arithmetic unit 2, and partially the same instruction and a different instruction can be executed, providing flexibility in calculation. be able to.

This allows a single-instruction type parallel computer to operate like a multiple-instruction type parallel computer.

[Problem to be solved by the invention]

However, in order to perform arithmetic processing using different instructions for each arithmetic unit in a conventional single-instruction type parallel computer, it is necessary to perform the following operations the same number of times as the number of instructions. In other words, only the operation permission flag of the arithmetic device that wants to execute a certain instruction is set to the permission state, and only the arithmetic device that is allowed to operate executes the desired arithmetic processing, and other arithmetic devices skip that instruction and do not perform the arithmetic processing. This is the action.

By repeating this for the number of instructions, even a single-instruction type parallel computer can perform arithmetic processing equivalent to a multiple-instruction type parallel computer. However, this procedure can be executed in one step in a multi-instruction type parallel computer, but in a conventional single-instruction type parallel computer, steps equal to the number of instructions are required, which takes a long time and is not practical. there were.

The present invention was made in view of the above circumstances, and it is possible to simplify the process by providing an instruction register in the arithmetic unit to store local instructions, and selectively executing this and a common instruction from the control circuit. It is an object of the present invention to provide a single-instruction type parallel computer that can process multiple instructions at high speed like a multiple-instruction type parallel computer while retaining the hardware features of a simple configuration and low cost.

[Means to solve the problem]

A single-instruction type parallel computer according to the present invention is a single-instruction type parallel computer in which a common instruction is given from a control circuit to a plurality of arithmetic units equipped with an arithmetic unit and a memory, and the given instructions are executed in parallel. The arithmetic device includes an instruction storage means for storing a local instruction, a selection means for selecting either the common instruction or the local instruction stored in the instruction storage means, and a selection means for selecting one of the common instruction and the local instruction stored in the instruction storage means. The present invention is characterized by comprising a selection control means for controlling a selection operation and a means for executing a selected command.

[Effect]

In the present invention, when a plurality of instructions are executed in parallel by an arithmetic unit, the local instruction is stored in the instruction storage means, and the selection means is configured to select either the local instruction or the common instruction. Each arithmetic unit is controlled and a selected instruction is executed; for example, when an addition instruction and a subtraction instruction are executed in parallel, the addition instruction is used as a common instruction and is given to each arithmetic unit from the control circuit. At this time, the subtraction instruction is stored in the instruction storage means of the arithmetic unit that executes the subtraction instruction, which is a local instruction, and the selection means of the arithmetic unit that executes the addition instruction selects the addition instruction by the selection control means. The selection means of the arithmetic unit which is controlled and executes the subtraction instruction is conversely controlled to select the subtraction instruction within the instruction storage means. This allows a single-instruction type parallel computer to simultaneously execute multiple instructions in parallel, reducing processing time.

〔Example〕

Hereinafter, the present invention will be explained based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of an arithmetic unit 2 of a single-instruction type parallel computer according to the present invention. Note that the overall configuration is the same as that of the conventional example shown in FIG. 2, and a description thereof will be omitted.

An instruction INS applied from the control circuit 1 (see FIG. 2) via an instruction bus 12 is applied to one end of a selector 26, which is selection means. The other end of the selector 26 is given an instruction IN5P stored in an instruction register 27 which is an instruction storage means. The instruction register 27 is part of register group 2, which will be described later.
1, and stores the local instruction IN5P generated by the arithmetic unit 22. The selector 26 selects one of the two received instructions INS and lN5P, and supplies the selected instruction INS or rNsP to the arithmetic unit 22. The selection operation of the selector 26 is controlled by an instruction selection circuit 25 which is selection control means. The command selection circuit 25 receives a control signal CTR applied from the control circuit 1 via the control line 11.
and an operation permission flag 24 to be described later, and outputs a switching signal CS to the selector 26 based on the control signal CTR and the state of the operation permission flag 24.

The arithmetic unit 22 performs arithmetic processing according to a given command.

For example, when storing an instruction IN5P in the instruction register 27, such an instruction INS is sent from the control circuit 1 to the selector 26.
It reads data from the local memory 23, generates the necessary instruction IN5P, and stores it in the instruction register 27 in the register group 21.

On the other hand, address 800 given from control circuit 1 via address bus 13 is given to local memory 23 or register group 21. The local memory 23 is the computing unit 22
The register group 21 temporarily stores the calculation data stored in the local memory 23 and the data in the middle of the calculation, and provides the data to the calculation unit 22.

Further, the register group 21 has an area for storing an operation permission flag 24 indicating which instruction of the selector 26 is selected depending on the state of the arithmetic device 2, whether the operation is permitted or not, and when the operation is permitted. An instruction register 27 is provided to store the local instruction IN5P generated by the arithmetic unit 22.

In the single-instruction type parallel computer of the present invention configured as described above, each arithmetic unit 2, 2, . execute the common instruction INS stored in the instruction register 27, or execute the local instruction IN stored in the instruction register 27.
The selector 26 selects whether to execute 5P and executes the selected instruction.

If addition and subtraction are to be executed simultaneously in parallel, for example, the addition instruction is a common instruction INS, and the subtraction instruction is a local instruction IN5P. In order to first generate a subtraction instruction, the control circuit 1 controls each arithmetic unit 2, 2, . . .
Give an instruction to generate a subtraction instruction. At this time, the operation permission flag 24 of each arithmetic device 2, 2... is in the permission state,
In response to the control signal CTR, the instruction selection circuit 25 outputs a switching signal CS so that the selector 26 selects the instruction INS. On the other hand, at this time, the address AD of the location where the data for generating the subtraction instruction is stored is sent from the control circuit 1 to the local memory 23 via the address bus 13.
At the same time that D is output, the address of the instruction register 27 is output to the register group 21.

Then, the arithmetic unit 22 generates a subtraction instruction and stores it in the instruction register 27. Subsequently, the control signal CTR sets the operation permission flag 24 to a value indicating permission, non-permission, and selection by the selector 26 in the case of permission. When performing addition and subtraction, all arithmetic units 2, 2, . . . are enabled to operate, and the addition instruction is executed. Arithmetic device 2, 2・
... is connected to the control circuit 1, and arithmetic units 2, 2, ..., which execute the subtraction instruction, are connected to the instruction register 27, respectively.
6 is set in the operation permission flag 24. Next, a control signal CTR is applied to the instruction selection circuit 25, and either all the arithmetic units 2, 2, . . . Execute the instruction INS from
and the other executes the instruction INS from the control circuit 1.

In this case, the third pattern is determined by the control signal CTR, the operation permission flag 24 is set to the value as described above, an addition instruction is given from the control circuit 1, and a subtraction instruction is given from the instruction register 27.

In this manner, the present invention enables the execution of instructions unique to each arithmetic unit in addition to the execution of a single instruction as in the conventional case.

Further, the instruction selection circuit 25 allows the instruction selection circuit 25 to determine whether the instruction to be executed is obtained from a common instruction or from a unique instruction register 27. This choice reduces the frequency of instruction generation. That is, when two instructions are selectively executed, one instruction is obtained from a common instruction.
The generation of instructions to be stored in the instruction register 27 only requires other instructions.

[Effects] As explained above, the present invention includes: an instruction storage means for storing local instructions in an arithmetic device; a selection means for selecting either a common instruction or a local instruction;
and a selection control means for controlling the selection operation of the selection means,
Since the instruction to be executed can be selected by the selection means, a plurality of instructions can be simultaneously executed in parallel while retaining the features of a single instruction type, and an equivalent effect of shortening processing time can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an arithmetic unit of a single-instruction parallel computer according to the present invention, FIG. 2 is a schematic block diagram showing the overall configuration of a conventional parallel computer, and FIG. 3 is a conventional arithmetic unit. FIG. 2 is a block diagram showing the configuration of FIG.

Claims (1)

[Claims] 1. In a single-instruction type parallel computer that gives a common instruction from a control circuit to a plurality of arithmetic units each including an arithmetic unit and a memory, and executes the given instructions in parallel, the arithmetic unit comprises: , instruction storage means for storing a local instruction; selection means for selecting either the common instruction or the local instruction stored in the instruction storage means; and controlling the selection operation of the selection means. 1. A single-instruction type parallel computer, comprising: selection control means for executing the selected instruction; and means for executing the selected instruction.