JPS62208158A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To increase processing speed and to provide the titled system with diversity by connecting bus control circuits like shift registers between respective processor components and processor devices consisting of local memories to form a ring bus. CONSTITUTION:The bus control circuit 4 is provided between respective processor components 3 and local memories 2 and plural bus control circuit are connected like shift registers. The shift registers from the ring bus 1 and are controlled by a ring bus control circuit 8. The whole system is controlled by a microcomputer 5 and connected to a host computer through a system bus 10 and an interface part 9 for I/O. The ring bus 1 can be used for executing the I/O of an image from/to an external equipments at high speed and can attain may operation modes.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a multi-processing system for performing information processing at high speed, and is particularly suitable for high-speed parallel processing of two-dimensional data such as images. Regarding multi-process systems.

<Prior Art> Image processing requires a large computational capacity that cannot be achieved by a single processor, so various multiprocessor type image processors have been proposed. In traditional multiprocessors.

We focused on the level of preprocessing such as filtering, which is simple but requires ultra-high-speed calculations. In that case, 1982
An LSI Adaptive Array Processor (An LSI
Adaptive Array Processes
It is called a fully parallel type, in which there are only two processors for each pixel, such as the sor), and each processor has one processor.
Although it only had a low function of bit calculation, many configurations were used in which high speed was achieved by arranging a large number of them. And regarding image feature extraction and structural analysis, which are higher-level processing.

The methods used were either to sacrifice speed and rely on general-purpose microcontroller programs (which could use advanced arithmetic instructions), or to individually design and use specialized hardware for limited purposes.

However, as the field of application of image processors expands, the required processing is also becoming more sophisticated. In other words, increasing the speed of preprocessing alone is meaningless, and processors that can handle higher levels are now required.

In response to this, the earlier application (Japanese Patent Publication No. 59-14
0456), by connecting multiple processors with advanced functionality in a ring.

We have provided a method that enables high-speed and complex processing.

Problems to be solved by the present invention> When increasing computing power with a multiprocessor model.

There is a problem in that the communication between processors or the sharing and exchange of data between processors creates overhead, making it impossible to obtain the expected performance. In addition to this general problem, in two-image processing, it is necessary to be able to transfer data at high speed between two-dimensionally adjacent processors1.For example, in the fully parallel multiprocessor system mentioned above, all The processors are connected so that data can be transferred to eight adjacent processors. As a result, the scale of the circuit increases, the arithmetic function is limited to 1 bit, and data transfer can only be performed on a 1-bit basis, although preprocessing can be performed at high speed.

It was unsuitable for advanced image processing.

On the other hand, this is the earlier application mentioned above. The method of connecting processors in a ring was devised to prevent an increase in the size of one circuit. However, in the control method shown in the embodiment, in order to synchronize the data flowing on the ring bus with the processing of the processor, the control section judges the status of each of them, and then sequentially processes the processor and the processor. Because it uses a method of sending control commands to the ring bus control unit, it was not possible to achieve sufficient high speed.

An object of the present invention is to realize an economical and practical ultra-high performance image processor by adding innovation to the connection method when a plurality of processors are used.

Means for Solving the Problems> The overall configuration of the present invention is shown in FIG. 1. A processor unit (PU) 20 indicated by a broken line in FIG. Loca
lMe+mory) 2, which are arranged in multiple sets. However, in Figure 1, in order to make the diagram easier to read, only one PU 20 (1) is shown with a broken line, and for other PUs, the dashed line and symbols 20 (2), 20 (64), etc. are omitted. be.

between each PE3 and local memory 2.

Contains a bus control circuit (Path Ctl) 4,
The 64 bus control circuits are connected like a shift register. Also, this shift register is connected to a ring bus (Ring bus).
The ring bus control circuit (Ring l1us Ctl,) 8 forms a ring bus control circuit (Ring l1us Ctl, ) 8.

And the whole is a microcomputer (68000) 5
and is connected to a host computer via a system bus 1o and an interface section (DMA I/F and PIO I/F) 9 for input/output.

The ring bus 1 is also used to input and output images to and from external devices at high speed. Furthermore, according to the present invention, P
The number of U can be arbitrarily selected and can be freely increased or decreased according to the required processing capacity.

<Operation> In the present invention, the hardware connection of the PUs is a one-dimensional ring bus connection (which is considered not advantageous for image processing). This is because the structure is simple, making it suitable for miniaturization in terms of hardware.

The transfer data φt5 can be as wide as 1 word (16 bits). Also, even if the physical connection is one-dimensional, logically (
This is because it can be handled as an arbitrary two-dimensional array (such as 8x8, 4x16, 2x32), so it has the advantage of having a higher degree of freedom (compared to 8-way connections).

Furthermore, by providing the ring bus 1 at the connection point between the processor element 3 and the local memory 2, it is possible to realize various operating modes, which will be described in detail in the embodiments.
Furthermore, the ring bus is used only to transfer data, and the address and read/write signals to the local memory are supplied from the PE (by program), eliminating hardware such as address counters and reducing the circuit size. At the same time, it has automated the synchronization of data flow on the ring bus and processor processing, making it possible to execute processing at high speed.

<Example> An embodiment of the present invention will be described below.

1. In this embodiment, 64M1 of the same circuit configuration are used for the PU20, so 2. If there is any significance in the number of these, 20(1) or 23M1 is used.
It is written using parentheses, such as (2), and when referring to one of them, it is written without the parentheses, such as 20 or 23.

[Four Operation Modes] In the present invention, as shown in FIG.
) to 20 (64) local memory 2 (1) to 2 (64
).

In addition, each PE3 (1) to PE3 (64) has an independent dedicated program memory therein, and the contents (programs) are stored in the system memory (System+* Memory) 6
DMA controller (DMAC) as needed.
Transferred by 7. At this time, the same program can be transferred to all PEs at the same time. And PE3
The microprocessor (68000) 5 controls starting and stopping from an arbitrary address, and each PE 3 can interrupt the microprocessor 5 when necessary.

By the way, in the present invention, since images are processed by a plurality of PUs 20, nine image data and processing programs are distributed to each PU in some way.

It is important to perform parallel processing efficiently. As a versatile image processor, it can execute a wide variety of image processing algorithms without any problems.

In this example, four operation modes (usage forms) are shown in Table 1.
The operation mode was set to function. These are summarized in Table 1. Each mode will be explained below.

(a) Multiple data mode When multiple images can be distributed to multiple PUs, such as when there are images to be processed in a large area and the same processing is applied to them sequentially, this mode allows you to There is almost no overhead as there is no need to exchange data between the PUs.However, when the processing end times of multiple PUs coincide, there will be a conflict between the ring buses that supply two image data to the local memory, resulting in a wait. Care must be taken (actually, the end time of the PU is moderately randomized, so it does not result in a large overhead).

(b) Region division mode This mode is used when it is desired to process one image at high speed. However, since the 9 images are divided into partial areas and distributed to each PU for processing (see Figure 4), when the series of processing is completed, the processing results are connected on the boundary line between the two partial areas. may be necessary. This is extra processing specific to the area division mode, and if this processing method is executed carelessly, there is a risk of causing a large overhead. However, as will be detailed later, according to the configuration of the present invention,
The time required for such processing can be kept sufficiently small so as not to cause overhead.

(c) Functional division mode This mode is a processing algorithm that allows the processing functions to be divided among multiple PUs when calculating a large number of features or performing matching with a large number of dictionaries for one target image. suitable for in this case.

Since the amount of data obtained as a result of the processing is much smaller than the amount of data for a 9-original image, the process of accumulating the processing results distributed to each PU cannot be called overhead.

(d) Pipeline mode In this mode, the image signal obtained from a scanner is
This method is suitable when the pixel data generated is slow and can be processed in real time in accordance with this data rate, and when the processing content is divided into a plurality of sequential functions.

[Configuration of the ring bus section] IP of the bus control circuit (Path Ctl,) 4 on the ring bus 1 shown in Fig. 1
The details for U are shown in Figure 2. The path control circuit has two types of latches (data latch 21 and flag latch 22), each of which is connected like a shift register to a similar latch of an adjacent PU. Together with the bus control section 8, the ring bus is configured as a whole.

That is, the data latch 21 and the flag latch 22 operate as a shift register by updating data every time they receive the shift clock 14, and transfer data in a ring shape as a whole of 64 sets.

Based on FIG. 2, the flow of data will first be explained.

The data to 16-bit 1 sent from the data latch in the next stage is sent to the data bus control unit (DataBus Ctl).
,) enters 23. Here, data bus 10 of PE3
1 and local memory 2 are connected to data buses 102 and 103 (each having a width of 16 bits). Further, there is a data latch 21 belonging to that stage, and the data bus control unit 23, which goes out to the next PU, has seven tri-state control gates 231 to 2 as shown in the figure.
37, which control gate is opened and which control gate is closed is determined by a select signal (Select S
signal) 104. The select signal is the read signal (RD) 1 output from PE3.
05, write signal (WT) 106. and an address bus (not shown in the figure), which select the seven types of connection states shown in FIG. All the image data transfers required for the four operation modes of this embodiment described above can be realized by selectively using these seven types of connection states.

In addition, the ring bus is used only to transfer data, and addresses and read/write signals to the local memory 2 are supplied from the PE 3 (by program), eliminating hardware such as address counters and reducing the number of circuits to 9. We are trying to downsize.

Next, the function of the flag latch will be explained.

As shown in FIG. 2, the output 108 of the flag latch is ANDed by the AND gate 25 with the signal 107 obtained by ORing the read/write signal (RD105.WT106) of PE3 by the OR gate 24, and the signal 108 is output from the ready pin of PE3. (RDY) 109. Therefore,
The read/write operation of PE3 is executed only when the flag latch 22 is set to 1, and the read/write operation of PE3 is delayed until the flag latch 22 becomes 1. The data 11 flowing through the data bus controller 23 of the desired PU 3
The flag latch 22 is set at the timing of reaching the PE3 program.
It is synchronized with the light operation. Note that the state of the flag latch is determined by the mode signal 12. sent from the ring bus control circuit 8. The flag control circuit (
FlagCtl, ) 26 is determined. in this way.

In the present invention, the synchronization of the data flow on the ring bus and the processing by the processor, which was a bottleneck in speeding up the processing in the method of the previous application, is automated and can be performed in an extremely short time.

[Considerations regarding area division mode] In area division mode, problems unique to this mode arise, which will be explained in detail here.

In this mode, as shown in FIG. 4, XXYii! An image of size ii is a partial image S of size of xxy pixels,
Divide into □. Then, these mXn partial images SIJ
is assigned to mXn PUs and processed. Therefore, when the processing to be executed is in units of two pixels, such as density conversion, mXn
You can get twice the speed. However, when the processing result of one pixel is determined by the data of a plurality of pixels included in a mask area centered on that pixel, as in the case of filtering processing, the situation becomes somewhat complicated. That is, as shown in FIG.

This is because the mask area centered on the pixel at the periphery of the image protrudes outside the two images.

Cannot be processed correctly (The part that cannot be processed correctly in this way is called the abnormal part)
This problem arises in image processing in general, but especially when processing in segmentation mode.

Since it is necessary to connect each partial image later to return it to its original size, the periphery of one partial image (i.e. the border)
It is fatal if abnormal parts occur.

In order to avoid this, in the region division mode, in Figure 6 (a)
), it is necessary to overlap the nine partial images in advance. Furthermore.

The width of the abnormal part (half the width of the mask area minus 1) that occurs around the partial image increases additively by repeating filtering, so it is necessary to prevent this. In other words.

It is necessary to replace the abnormal part with a normally processed image every time the filtering process is executed (or every few times it is repeated). This 1a transformation of the abnormal part can be realized as follows.If we look at the abnormal part generated by filtering the 0 partial image Slj between adjacent partial images, we can see the difference as shown in Fig. 7(,). , it can be seen that each is within the normally processed area of the other. Therefore, by using these normal image data of PUs adjacent in eight directions, the above replacement can be performed correctly.

By the way, when replacing an abnormal part, it is possible to do this in three directions without transferring the image data from the PUs in eight directions. In the previous explanation, since it is an intuitive and easy-to-understand processing method, a method was described in which pixels of the processing result are written at the center position of the mask area so that the position of the image after filtering processing is the same as before processing.

but.

If the resulting image is allowed to shift entirely relative to the pre-processing position, the processed pixel may be written in the upper left corner position of the mask area. As shown in FIG. 7(b), this occurs only on the right and downward sides. Therefore, data transfer for the above-mentioned replacement only needs to be performed in three directions instead of eight directions. In this case, the overlap area is taken as shown in Figure 6(b).The width of the abnormal area is the width of the mask area minus 1, but the number of pixels in the entire abnormal area is is the same as the former case; hereinafter, the former will be referred to as the 8-way transfer type and the latter as the 3-way transfer type.

[Control of Ring Bus in Area Division Mode] As described above, in the present invention, a plurality of PUs 20 are physically connected one-dimensionally by the ring bus 1. When using this in a two-dimensional area division mode as shown in FIG. 4, each PU is made to correspond to a logical two-dimensional arrangement (mXn). At this time, the connection relationship between the PUs is as shown in @8, which is actually well consistent with the mask scan of the image. Furthermore, the correspondence between the logical two-dimensional distance between PUs and the physical one-dimensional distance becomes simpler1.For example, data movement to the right in a logical two-dimensional space is performed using one ring bus. It is a shift of times.

Moving down is shifted by m times, moving to the upper left is (mn-n
-1) times, and this relationship holds true for all PU combinations. Two examples of ring bus control methods that take advantage of these features are shown below.

(a) Loading image data of partial images with overlap in area division mode is carried out via the ring bus control circuit 8 shown in FIG.
It is assumed that the data is sent from outside via raster scan.

■Reset the flag latches 22 of all PUs 20.

■ All PE3 have ? Increment 1 in order from the first address where 9 images should be written to local memory 2
Load and start the J program that writes the data from the ring bus 1 to the local memory 2 while generating the address for ~.■ Flag latch 22 (1) of the first PU3 (1)
The ring bus control circuit 8 only sends the image data to the cell 1 and 2.
The image data that is shifted onto the data latch 21 one after another is transferred to the ring bus 1 from the local memory 2 (1) of the first PU3 (1).
) only. During this time, the mode signal 12 is set to the hold mode, and all flag latches 22 are not changed. ■ Timing when the first pixel data that should be received by the second PU 20 (2) reaches the second PU 20 (2). In the copy 1 mode, which changes the mode signal 12 to the copy 1 mode and returns to the hold mode, the left flag latch 22 (i -
1) is 1, the flag latch 22(i
) is set to 1. As a result, the second flag latch 22(2) becomes 1 (the first flag latch 22(1) remains 1). If the image data continues to be shifted in this state, writing to the first and second local memories 2(1) and 2(2) will be performed in parallel. Sunaochi.

Overlapping writes are executed simultaneously.

and■ In that one raster, the first local memory 2 (1
), the mode signal 12 is set to copy 0 mode at the timing when the last pixel data of the data to be written passes through the first PU 20 (1). In the copy 0 mode, the left flag latch 22 (i-1) This means that the flag latch 22(i) is set to O only when it is 0. As a result, the first flag latch 22(1) becomes O, and the second flag latch 22(2) maintains 1.

If the shifting of image data is continued in this state, selective writing will be performed only in the second local memory 2 (2). From now on, the “1st” of ■■ will be changed to “i-1st” and “2nd”.
Replace "number day" with "rith" and advance ■i, turn ■ and ■ green in the same way as above, and set the i-th and i-1th flag latches 22(i) and 22(i-1). A grandchild of +mi PU20 (m)
When writing for one raster has been completed, the state returns to the initial state (■), and the image data of the subsequent raster is written one after the other. In the case of one-dimensional tanzag-shaped region division, distribution of all partial images is completed in this way, but in the case of two-dimensional region division.

Mode signal control similar to the above-mentioned horizontal direction control is also performed in the vertical direction.

(b) Replacement of abnormal parts in region division mode
All PE3s are loaded with a program that "repeats reading and then writing while updating the address of local memory 2." ■ All flag latches 22 are set to 1 once by mode signal 12. Set all flag latches 22 to 0 again by mode signal 12 (to postpone the write operation of PE3), and cause all PE3 to read data from local memory 2. Set all flag latches 22 to 1 again The transferred data is transferred to the local memory by the write operation of PE3. Written to 2. In this way, replacement for one pixel is completed. Thereafter, the same operation is repeated a predetermined number of times (the number of pixels determined as the product of the overlap radius and the length of one side of the partial image, see FIG. 7).

Up to this point, the replacement of pixel data in one direction is completed.

■ Change the number of ring bus shifts (used in ■) set in the ring bus control circuit 8.

Execute ■～■ again.

This completes the replacement in two directions, but all the actually necessary transfers for the three-way transfer type have been completed so far, and the third transfer is unnecessary. because.

The normal data of S + +1101 shown in Figure 7 during the first replacement (assuming that the transfer to the left is then transferred upward) is transferred to 5Ij (1), and this is transferred to the second replacement. This is because the data can be transferred to Sl together with the normal data in SiJ+1.

As can be seen from the above explanation, replacement of abnormal parts in region division mode can be done by using ring bus 1.
Since the process can be performed in parallel for all the plurality of PUs 3, it is completed in a short time regardless of the number of PUs 3.

According to the same control method, simultaneous loading of the same image to a plurality of PUs 3 can be executed extremely quickly since the image data is delivered to all PUs 3 by simply loading it onto the ring bus 1 once.

As shown in FIG. 9, the ring bus control circuit 8 has a shift I.
Control unit 81 and selector 82. The 1 normal selector 82, which is composed of an input buffer 83 and an output buffer 84, is connected so that the ring bus data 11 (64) goes out to 11 (0). 82 is switched by a signal from the system bus 10, and data coming in via the input bus sofa is sent to the ring bus as ring bus data 11(0). To output image data to a printer or the like, ring bus data 11 (64) is taken out to the outside via an output buffer 784.

The shift control unit 81 is provided with registers that store the vertical and horizontal numbers m and n of PUs placed in a logical two-dimensional arrangement, the overlap width of the divided images, and the like. is set by the microcomputer 5 before starting transfer on the ring bus 1. In addition to the above-mentioned registers, the shift control section 81 also includes a shift clock generator and a shift clock 14.
It consists of a counter that changes the mode signal 12 one after another based on these count values and the values set in the register, but if you understand the control method described above, Since this can be easily realized using various methods, details will be omitted.

<Effects of the Invention> According to the present invention, it is possible to speed up the exchange of data between processors, so that the processing speed in a multiprocessor can be significantly improved. Furthermore, since the processors are connected in a one-dimensional manner, the device size is small and practical. By placing a ring bus that connects processors between processors and local memory, it has become possible to realize many operating modes, and also to synchronize data flow and processor processing, and to generate memory addresses. The method is now simpler and faster.

[Brief Description of the Drawings] Fig. 1 is an embodiment of the present invention, Figs. 2 and 3 are diagrams showing details of the bus control circuit, Fig. 4 is an explanatory diagram of image division, and Figs. FIG. 8 is a diagram explaining the operating principle, and FIG. 9 is a diagram showing details of the ring bus control circuit. Explanation of symbols 1...Ring bus 2...Local memory 3...Processor element (PE) 4...Bus control circuit 5...Microcomputer 8...Ring bus control circuit

Claims (2)

[Claims] (1) A path control circuit consisting of a circuit that arranges multiple sets of processor units each consisting of a processor element and its local memory, and switches at least the data transfer direction between each processor unit and the local memory, and a data latch. 1. A multiprocessor system comprising: a multiprocessor system, wherein the data latches of the path control circuits are connected to each other like a shift register. (2) A plurality of processor units each consisting of a processor element and its local memory are arranged, and a circuit for switching at least the data transfer direction between each processor unit and the local memory, a data latch, and a flag latch is provided. The data latches of the path control circuit are connected to each other like a shift register, and the flag latch is connected to the processor.
A multiprocessor system characterized by being connected to a memory access control unit of an element.