JPH0642229B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a high-speed arithmetic unit in an information processing apparatus, and more particularly to a system configuration thereof.

[Problems to be Solved by Prior Art and Invention]

Conventionally, two types of high-speed arithmetic processors are known, an independent processor type and an attached processor type.

The high-speed processor of the independent processor type achieves high speed by the highly parallel operation mechanism such as vector operation, but it is difficult to parallelize the input / output and the accompanying edit processing in the execution of normal programs. However, there is a drawback that the parallel operation mechanism does not work effectively when executing such a part.

The attached processor-type high-speed arithmetic unit has a high-speed arithmetic memory suitable for high-speed arithmetic, but for input / output processing, data must be transferred between the arithmetic memory and control memory using channels, etc. It had the drawback of being difficult.

[Means for solving problems]

An object of the present invention is to eliminate the above drawbacks by configuring a high-speed arithmetic unit with a control processor and an arithmetic processor, and making the arithmetic memory appear as the same memory space as the control memory to the control processor and the input / output processor.
An object of the present invention is to provide an information processing device capable of executing arithmetic processing and input / output editing processing in parallel.

An information processing apparatus according to the present invention includes a system controller, a control processor, an input / output processor, an arithmetic processor, and a control memory connected to the system controller. The arithmetic memory is connected to the arithmetic processor, and the control processor and the input processor. From the output processor, the control memory and the arithmetic memory can be seen as one memory space, and from the arithmetic processor, the control memory and the arithmetic memory can be seen as different spaces. More specifically, the arithmetic processor has a boundary register that holds the capacity of the control memory and a subtractor, and a boundary address is subtracted from a request address in response to the arithmetic memory request from the system controller. The subtracted value is used as the address of the arithmetic memory.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, a system control device 1 includes a control processor 2 and an input / output processor 3 as a first processor group, an arithmetic processor 5 as a second processor group, and a first processor group. Are connected to the control memory 4 as the memory of each. The arithmetic memory 6 as the second memory is connected to the arithmetic processor 5. Memory requests of the control processor 2 and the input / output processor 3 are sent to the control memory 4 or the arithmetic processor 5 via the multiplexer 11 and the demultiplexer 12. The boundary register 10 is connected to the demultiplexer 12. The control memory request of the instruction processing unit 51 inside the arithmetic processor 5 is connected to the multiplexer 11 of the system controller 1, and the arithmetic memory request is connected to the multiplexer 53. The arithmetic memory request from the system controller 1 is sent to the subtractor 52 in the arithmetic processor 5.
And via the multiplexer 53, it is connected to the arithmetic memory 6. The other input of the subtractor 52 is the boundary register 5
Connected to 0. Write data and read data for completing the memory access are not shown in the figure. Also, other units such as the arithmetic unit in the arithmetic processor 5 are not shown in the figure.

It is assumed that the capacity of the control memory 4 is M and the capacity of the arithmetic memory 6 is N. The memory request of the control processor 2 is selected by the multiplexer 11 and guided to the demultiplexer 12. In the demultiplexer 12, the memory address is compared with the value M of the boundary register 10, and if the memory address is less than M, a memory request is issued to the control memory 4.
If the memory address is M or higher, a memory request is issued to the arithmetic processor 5. In the arithmetic processor 5, the subtracter 52 subtracts the value M of the boundary register from the request address, and the memory request is sent to the arithmetic memory 6 via the multiplexer 53. The memory request of the input / output processor 3 is similarly processed.

The control memory access of the arithmetic processor 5 is issued from the instruction processing unit 51 and guided to the multiplexer 11 of the system controller 1. Then, it is processed in the same manner as the memory request of the control processor 2 and sent to the control memory 4. The arithmetic memory request issued from the instruction processing unit 51 is sent directly to the arithmetic memory 6 via the multiplexer 53.

As shown in FIG. 2, from the control processor 2 and the input / output processor 3, the control memory 4 and the arithmetic memory 6 appear as one memory having an address space of M + N capacity, and from the arithmetic processor 5, M and N, respectively. It looks like two memories with an address space of N capacity.

The control processor 2 and the input / output processor 3 are the control memory 4
Since it is not necessary to be aware of the distinction between the operation memory 6 and the operation memory 6, programming of input / output and input / output editing is easy. To the arithmetic processor 5, the control memory 4 and the arithmetic memory 6 appear to be different memories, so that the arithmetic memory 6 can be designed independently of the control memory 4 to be suitable for high-speed arithmetic.

〔The invention's effect〕

As described above, the present invention facilitates a system that executes arithmetic processing and input / output editing processing in parallel by configuring the arithmetic memory so that the control processor and the input / output processor can see the same memory space as the control memory. There is an effect that can be provided to.

[Brief description of drawings]

FIG. 1 is a block diagram partially showing an embodiment of the present invention,
FIG. 2 is a diagram showing a state of the address space of the control memory 4 and the arithmetic memory 6 of FIG. 1 ... System control device, 2 ... Control processor, 3 ...
I / O processor, 4 ... Control memory, 5 ... Arithmetic processor, 6 ... Arithmetic memory, 10 ... Boundary register,
11 ... Multiplexer, 12 ... Demultiplexer,
50 ... Boundary register, 51 ... Instruction processing unit, 5
2 ... Subtractor, 53 ... Multiplexer.

Claims (1)

[Claims] 1. A system control device comprising a first processor group, a second processor group, and a first memory connected to the system control device, wherein the second processor group includes a second processor group.
In the information processing device to which the above memory is connected, the second processor group has a boundary register that holds the capacity of the first memory and a subtractor, and the second processor group transfers to the second memory. The information processing apparatus, wherein a value obtained by subtracting the value of the boundary register from the request address in response to the request is used as the address of the second memory.