JPS6011969A - Memory device with logical arithmetic means - Google Patents

Abstract

PURPOSE:To reduce the number of accesses given to a picture memory device from a CPU and to shorten the picture processing time by providing a logical calculating means to the memory device itself. CONSTITUTION:Old picture information read out of a memory element 47 is applied to an input 2 of a logical arithmetic means 40. At the same time, qualification information given from a CPU is applied to an input 1 of the means 40. In this case, an output buffer 49 is inactivated to avoid the interference between the output given from the element 47 and the input given from a signal bus 5. The means 40 receives the logical calculation information from the bus 5 and changes old contents of a picture memory based on the contents of logical calculation information. The changed contents are given to the element 47 via a buffer 48 and written there. Therefore just two accesses suffice to the memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device with a logic operation mechanism that improves processing speed by attaching an operation mechanism to the memory itself that stores image contents in a computer used for image processing. .

Conventionally, there have been devices of this type as shown in FIGS. 1 and 2. FIG. 1 shows the overall configuration, and FIG. 2 is a block diagram showing the detailed configuration of the image memory device in FIG. 1.

First, in FIG. 1, 1 is a central processing unit (hereinafter, CP
2 is another input/output device, 3 is a memory device that stores programs, 4 is a memory device that stores image contents, and 5 is a high-speed signal bus that connects them all (hereinafter, signal bus). ).

The memory device 4 shown in FIG. 2 includes a control section 46, a memory element 4
7. It is composed of buffers 48 and 49, and the control unit 46 controls writing and reading of the memory element 47 based on the control signal from the signal bus 5, and the read contents of the memory element 47 are transferred to the buffer 48 and 49. 49 to the signal bus 5, and the write information on the signal bus 5 is written to the memory element 47 via the buffer 48.

Therefore, the buffer 48 is a memory write information buffer s5, and the buffer 49 is a read buffer.

Next, the operation will be explained. Write information output from the CPU and the human output device 2 is written to the memory device 3 if it is information related to a program, and to the memory device 4 if it is related to image information, through the signal path 5.

In the case of image information, the write information from the signal bus 5 is applied to the memory element 47 in FIG.

Normally, new image information is rarely far different from old image information, and new image information is obtained by performing a logical sum, logical product, or exclusive logical sum of old image information and certain information. The CPU reads a program from the memory device i\3 for program memory, reads old image information from the memory device 4 for image memory according to the content of the program, and then reads the old image information from the memory device 4 for image memory to perform the next processing content. Read the following program,
Depending on the content, the old image information is changed to new image information, and then the new image information is written into the memory device 4.

Since the conventional image memory device is configured as described above, in order to change old image information to new image information, CPU 1 needs to change memory device P (3 times twice, memory device 4 twice, This method has the disadvantage that the total memory device must be accessed four times, which increases the processing time.

This invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and by providing the image memory device h' itself with a logical calculation mechanism, accesses to the memory device by the CPU can be reduced, and image The object of the present invention is to provide a memory device with a logic operation mechanism that can reduce the time required for the part Jl[j.

Hereinafter, an embodiment of the logic operation mechanism (=j memory device h/4) of the present invention will be explained based on the drawings. FIG. 3 is a block diagram showing the configuration of one embodiment. 2, and to avoid duplication, the second
Parts that are the same as those in the figures are given the same reference numerals and their explanations are omitted.
We will focus on the parts that differ from those in Figure 2.

As is clear from comparing this Figure 3 with Figure 2,
In the figure, a logic operation mechanism 40 is newly provided. In order to provide new image information to the memory element 47, this logical operation mechanism 40 performs a logical operation on the old image information from the memory element 47 and the image information from the CPUI, and sends the new image information to the memory element 47 through the buffer 48. It is given to

Next, the operation of the memory device with logic operation mechanism of the present invention configured as described above will be explained.

In FIG. 1, when the CPUI reads the memory device 3 storing the program and changes the image memory contents depending on the contents, the modification information for the old image contents is immediately changed without reading out the old image contents. ,
The logic calculation information is provided via a signal bus 5 to a memory device 4 which stores the image content.

In the memory device w4, the old image information read from the memory element 47 is added to the input 2 of the logic operation unit 40, and the modification information from the CPUI is added to the input 1 of the logic operation unit 40. At this time, by inactivating the output buffer 49, the output from the memory element 47 and the signal bus 5 are
to prevent input from interfering with each other.

The logical arithmetic unit 40 receives the logical deletion n-ffi information from the signal bus 5, changes the contents of the old image memory to its contents, and supplies the information to the memory element 47 through the buffer 48 for writing. Therefore, the conventional J4M memory device needs to be accessed four times, but with the present invention, it only needs to be accessed two times.

As described above, according to the memory device used to publish the logic calculator 41''I' of the present invention, the memory device itself that stores the image content is equipped with an arithmetic mechanism. The image memory contents are added from the memory element to the logic operation mechanism, and the modification information is added to the logic operation mechanism from the bus, and the old image memory contents are changed based on the logic operation mechanism and written to the memory element. ,
Writing to a memory device that stores image contents can be performed by the memory device itself without going through the CPU, which has the effect of improving processing speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the connection relationship between a conventional CPU and a memory device, FIG. 2 is a diagram showing a detailed configuration of the memory device that stores the image contents in FIG. 1, and FIG. 3 is a diagram showing the logical operation of the present invention. 1 is a block diagram showing the configuration of an embodiment of a memory device with mechanism. FIG. 1... Central processing unit, 2... Input/output device, 3, 4.
...Memory device, 5...Signal bus, 46...Control unit, 47...Memory element, 48.49...Buffer,
400. , logical operation mechanism. In addition, the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A logic operation mechanism is provided in the writing circuit of a memory device that stores image contents of a computer that performs image processing, and when writing new image contents to the memory device, it is possible to write the old image contents stored in this memory device and the new image contents. A memory device with a logic operation mechanism, characterized in that the image information is input to the logic operation mechanism, a logical operation is performed based on the logic calculation information, and new image information is written in the memory device.