JPS5855536B2 - Common memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common memory control circuit used when two central processing units share memory.

For example, the tasks to be processed by an arithmetic and control device for controlling the process of a product manufacturing line in an article manufacturing factory can be broadly classified as follows.

[F] Data calculation processing, ■ Control of peripheral terminal devices, ■ Data communication with host computer, ■ Input/output of process control equipment (digital input/output, analog input/output), ■ Sequence control of process control equipment (digital input/output) , by analog input/output) Here, the programs for processing the tasks (1) to (3) above are generally created by the manufacturer of this arithmetic and control device.

Therefore, as a programming language for creating this program, a normal programming language such as assembler or basic BASIC can be used.

-Programs for processing the work described in (1) above are generally created or modified by the user.

In this case, it is desirable for the user to be able to create a program for processing the task (2) using the same concept as the conventional recreation system.

That is, it is desirable that the programming language used here be a dedicated sequence control language that can be easily understood by comparing it with relay symbols.

Furthermore, sequence control executed by a program created using this type of sequence control language generally requires extremely fast response speed.

Therefore, in general, a program created using a sequence control language and a program created using a normal programming language are mixed in one program, and these programs are integrated into one central processing unit (hereinafter referred to as CPU). It is unreasonable in terms of processing speed, etc. to execute the process using

In other words, in this case, sequence control may not be executed correctly.

Therefore, in such a case, a CPU that executes a program created using a normal programming language and a CPU that executes a program created using sequence control terms, for example, are provided separately, and these CPUs are stored in a common memory. It is desirable to run a plurality of programs created using different types of programming languages in parallel by connecting them via a .

In such a case, a common memory control circuit is required to control access to the common memory between the two CPUs and the common memory, but this common memory control circuit has a quick access response. It must be a circuit, and it is desirable that the configuration be simple.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a common memory control circuit that can be simplified in configuration and has a quick access response.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a process control system using a common memory control circuit, which is an embodiment of the present invention.

In this figure, the part indicated by the symbol A is an arithmetic control device, and in this arithmetic control device A, 1 is a first CPU 1
Reference numeral 2 denotes a dedicated memory in which programs created using a normal programming language (for example, assembler, basic, etc.) used by the CPU 1 are stored.

Further, 3 is a second CPU, and 4 is a dedicated memory in which a program created using a sequence control language used by this CPU 3 is stored.

Further, the CPUI 3 can access the common memory 5 (write and read data) via common memory controllers la and 3a (common memory control circuit) added thereto.

Next, the signal bus 6 of the CPU 1 includes a printer control interface 7, a CRT control interface 8, a host computer interface 9, and a digital input/output device 10.
, analog input/output device 11 are connected, and the printer control interface 7, CRTff? 1Jffll
A printer 12, a cathode ray tube display (CRT) 13, and a host computer 14 for managing the CPU 1 are connected to the interface 8 and the host computer interface 9, respectively.

Further, the signal bus 15 of the CPU 3 includes a plurality of digital input/output devices 16. which input/output only digital signals used for sequence control in this process control system. . . . and a plurality of analog input/output devices 17, . . . which input/output only analog signals used for sequence control.

Here, the CPU 1.3 and the common memory controller 1
The arithmetic and control unit A, which includes the common memory 5, etc., will be explained in more detail with reference to FIG.

In the CPU 1 in FIG. 2, a binary logic signal "1" is supplied to the terminal REDY when the common memory 5 connected to the CPU 1 is in a state where data can be read or written, and when it is not in a state where it is possible to read or write data. If ゛°0″
The input terminal to which the signal is supplied, the terminal ADD1 is the output terminal that outputs the address signal, the terminal DAT1 is the input/output terminal that inputs and outputs the data signal, and the terminal 5TBI is the data strobe signal ("1'" for the write command). This is an output terminal that outputs a pulse signal.

Next, in the CPU 3, the terminal HLD is an input terminal to which a "°1" signal is supplied only when the CPU 3 requests to prohibit the CPU 3 from accessing the memory 5.
The terminal HLDA outputs n 1 when the terminal HLD is supplied with the °1' signal and the CPU 3 accepts or accepts this prohibition request.
The terminal ADD2 is an output terminal that outputs an n signal, the terminal ADD2 is an output terminal that outputs an address signal, the terminal DAT2 is an input/output terminal that inputs and outputs a data signal, and the terminal 5TB2 is an output terminal that outputs a data strobe signal.

In the common memory 5, the terminal ADD3 is an input terminal for inputting an address signal, the terminal DAT3 is an input/output terminal for inputting/outputting a data signal, and the terminal 5TB3 is an input terminal for inputting a data strobe signal.

Next, in the common memory controllers 1a and 3a, 1
8゜19.20 are gates that open when a ``1'' signal is supplied to their input terminals E, and 21.22 open when a ``'1'' signal is supplied to their input terminals E. The bidirectional gate 23 outputs a "1' signal from its output terminal C when the address signal supplied from the terminal ADDI indicates an address area allocated to the common memory 5, and also outputs a "1' signal from its input terminal E. This gate circuit sends the address signal supplied from the terminal ADD1 to the terminal ADD3 when a "1'" signal is supplied.

24 is supplied to its input terminal R? It is reset at the rising edge of the +111 signal and is supplied to its input terminal S.
This is a flip-flop (hereinafter referred to as FF: switching control circuit) that is set at the rising edge of the 1' signal, and has input terminals R and S.
The falling edge of the signal supplied to and the level of this signal have no effect on the output.

Note that the output terminal Q is the output terminal on the set side.

Further, 25 is an inverter.

Next, the operation of the circuit shown in FIG. 2 will be explained.

First, the FF 24 is set in an initial state by a circuit not shown.

Here, if the address signal of the CPU 1 output from the terminal ADD1 does not indicate the address area of the common memory 5, the output terminal C of the gate circuit 23 is outputting the "'0" signal, so the terminal HLD The signal is the ``0'' signal, the signal supplied to the terminal REDY is the ``1'' signal, the terminal H
The signal output from the LDA is the "O" signal.

Therefore, in this case, gate 18, bidirectional gate 21 .
The gates of the gate circuit 23 are both closed, and the gates 19 and 2 are closed.
0, since both bidirectional gates 22 are in the open state, the CPU
3 can access the common memory 5.

Next, as shown in the time chart of FIG. 3, if the address signal of the CPU 1 output from the terminal ADD1 indicates the address area of the common memory 5 at time t1 (the diagonal line in the waveform A of FIG. Since the terminal C of the gate circuit 23 outputs the u111 signal, the signal at the terminal HLD of the CPU 3 becomes the "1" signal (see the opening in Figure 3), and since the FF 24 is reset, the
A '0°' signal is supplied to the terminal REDY of PU1.

(See c in Figure 3).

As a result, the CPU 1 enters a state in which it has access to the common memory 5, and the CPU 3 enters a state in which access to the common memory 5 is requested to be prohibited.

Next, when the CPU 3 accepts the access prohibition request to the common memory 5 at time t2, the terminal HLDA outputs “1”.
” signal is output (see Figure 3, 2), FF24
is set and the signal supplied to the terminal REDY is °1
'', the gate 18, the bidirectional gate 21,
All gates of the gate circuit 23 are opened.

Also, at this time, since the output of the inverter 25 is a 000p signal, the gates 19 and 20 and the bidirectional gate 22 are all closed.

As a result, the CPU 1 is enabled to write data to or read data from the common memory 5, while the CPU 3 is prohibited from accessing the common memory 5.

Here, the CPU 1 writes data to the common memory 5,
Alternatively, data is read from the common memory 5.

Next, at time t3, when the CPUI completes access to the common memory 5, the signal output from the terminal C of the gate circuit 23 becomes the "°0" signal, and the terminal HL of the CPU1
Since the signal D becomes the "'0" signal, the request for inhibiting access to the common memory 5 to the CPU 3 is released.

Next, at time t4, the CPU 3 accepts the cancellation of this prohibition request and returns the signal at the terminal HLDA to the "O" signal.

As a result, both CPUs 1 and 3 are in the same state as before time t1.

In this manner, according to the configuration shown in FIG. 2, the CPUs 1 and 3 can use the common memory 5 as if it were a dedicated memory without interfering with each other's operations.

Next, the overall operation of the process control system shown in FIG. 1 will be explained.

The CPU 1 performs printing on the printer 12, displaying on the CRT 13, exchanging information with the host computer 14, and communicating via the digital input/output device 10 in accordance with the program stored in the memory 2 (a program created using a normal programming language). Input/output of digital signals used for purposes other than sequence control, input/output of analog signals used for purposes other than sequence control via the analog input/output device 11, and perform all data calculation processing other than sequence control in this process. , controls input/output of process data, etc.

On the other hand, the CPU 3 runs the program stored in the memory 4 (
program created using a sequence control language)
Accordingly, only sequence control in this process control system is performed via the digital input/output devices 16, . . . and analog input/output devices 17°, .

In this case, CPU1 uses common memory 5 from CPU3.
The necessary information can be read through the CPU.
3 can read necessary information from the CPU 1 via the common memory 5.

As described above, according to the process control system using the arithmetic control device according to this embodiment, access to the common memory 5 is quick, so that programs created using a normal programming language and a sequence control language can be used. It is possible to execute programs created in parallel with each other without interfering with the operations of each other's central processing units, thereby making it possible to control the entire process.

As explained above, according to the present invention, in the common memory control circuit that controls access to the common memory shared by the first and second central processing units, address information output by the first central processing unit is within the address range of the common memory, a gate circuit outputs an access prohibition request to the second CPU while the address information is being output; a switching control circuit that puts the central processing unit in a standby state and releases the first central processing unit from the standby state when the second central processing unit accepts the access prohibition request and outputs a response signal; Since it is equipped with the following, it is possible to configure it extremely easily and to obtain fast response.

Furthermore, since there is no burden on the program in each central processing unit, there is an advantage that the system is easy to create.

Therefore, it is particularly effective when two central processing units are made to execute in parallel a plurality of programs created using different types of programming languages.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example when an embodiment of the present invention is applied to a process control system, FIG. 2 is a block diagram showing details of an arithmetic and control device in the same embodiment, and FIG. It is a time chart for explaining an example. 1...First central processing unit, 1a, 3a
...Common memory controller (common memory control circuit), 3...Second central processing unit, 5...
...Common memory (common memory), 23...
- Gate circuit, 24...Flip-flop (switching control circuit).

Claims (1)

[Claims] 1. In a common memory control circuit that controls access to a common memory shared by first and second central processing units, when the address information output by the first central processing unit is within the address range of the common memory, a gate circuit that outputs an access prohibition request to the second CPU while the address information is output; and a gate circuit that puts the first central processing unit in a standby state at the same time as the access prohibition request is output; Common memory control characterized by comprising a switching control circuit that releases the standby state of the first central processing unit when the second central processing unit accepts the access prohibition request and outputs a response signal. circuit.