JPS5822470A - Arithmetic controller - Google Patents

Abstract

PURPOSE:To generate and maintain a program extremely easy by independently providing two CPUs which use mutually different program languages, and connecting those CPUs mutually through a common memory. CONSTITUTION:A CPU 1 inputs and output an analog signal for control other than sequence control according to a program generated by using normal program words and stored in a memory 2 to control data arithmetic processing, input and output of process data, etc. A CPU 3, on the other hand, performs only sequence control over this process control system according to a program generated by using a language for sequence control and stored in a memory 4. In this case, the CPUs 1 and 3 read necessary information through a common memory 5. Consequently, those two programs are executed in parallel without disturbing the opposite CPUs mutually, so the generation and maintenance of the programs are facilitated extremely.

Description

[Detailed description of the invention]

The present invention relates to an arithmetic control device that can execute a plurality of 10-grams created using different programming languages in parallel. For example, an arithmetic and control unit for controlling the process of manufacturing a product in an article manufacturing factory can be broadly classified into the following types of work: ■ Data calculation processing, ■ Control of peripheral terminal devices. ■ Data communication with the host computer, ■ Input/output of process data (digital input/output, analog input/output), ■ Sequence control of process control equipment (16 for digital input/output, analog input/output), It is common for the manufacturer of this arithmetic and control unit to create 10 grams to process all of the work in ■ib,
L-Therefore, when creating this program tube, there is a program language such as 1, for example assembler, and a normal program language such as Basic (BAS rQ).
can be used. - Generally, the program a to process the work in item (■) is created by the user or modified by the user.Part 1: In the case of leverage, for the user, rr is the program that processes all the work in item (i). Friendship program?
It is desirable that it can be created by anyone with the same idea as the conventional Nori V-Sikenst. I hope this is a language for sequence control! 1. In addition, extremely fast response speed is generally required for sequence control executed by programs created using this type of sequence control language. ,

[7 sentences generally refer to sequence control 1 term Wl
Programs created using k and regular programs 9 and 11
word? The program created using the program is mixed in one 1C1 gram, and this is used in one central processing unit (hereinafter referred to as C
PU and name) Therefore, it is impossible to execute the sequence control in terms of processing speed, etc. In this case, the sequence control may not be executed correctly. In view of the circumstances, this departure Ij1 has been rr-fc
Is a yt7 agram created using the first 10-gram language (e.g. a normal programming language)? 10 grams created using a running ACPU and a second programming language (for example, a sequence control language)? l! Provide separate CPUtt to run these CPUs? The trick is to connect via common memory. Different types of 10 Gura Goto II? It is an object of the present invention to provide an efficient arithmetic and control unit capable of executing multiple σ) programs created using the same method in parallel. Below is a drawing of an embodiment of this invention? Refer to and explain. FIG. 1 shows the block causes of a 10-process control system using an arithmetic and control unit according to an embodiment of the present invention. In this figure, the part indicated by the symbol A is an arithmetic and control unit, and in this arithmetic and control unit A, the %lσ first CPU
, 2rj What is the normal programming language used by this CPU 1 (for example, assembler, basic, etc.)? This is a dedicated memory in which programs created using the computer are stored. Further, 3 is a second CPU, and 4 is a dedicated memory in which a program created using the sequence control language used by the CPU 3 is stored. Also cptyt, 3σ
, a common memory controller la,3 added to them
Common memory 5 can be accessed via af (data can be written or read [7]?). Fin interface 8th place Convenience store I interface 9. Digital input/output device 10. Analog input/output! device 11 or connected, and the 19-meter control interface 7, CRT control interface 8. Upper computer interface 9 Kf'l printer 12 .CRT (cathode ray tube type #
screen display device)13. A host computer [4] that manages the CPUI is connected to each host computer. Furthermore, the signal bus 151C of the CPU 3 is connected to the sequence 11flJ II? in this process control system. Only digital signal input/output used to perform? A plurality of digital input/output devices 1116, . . . , and a plurality of analog input/output devices 17.・・・
・Is it connected? Here, an arithmetic control unit consisting of the CPUI 3, a common memory controller 4m, a common memory 5, etc.
1llA't - See Figure 21. This will be explained in more detail below. In the CPUxi in Figure @2, the terminal REDYσ,
If this CPUTVC-connected common memory 5 is in a data reading/writing enabled state, a binary logic signal "1" is supplied to lIr, and if it is not in a data writing enabled state, a "θ" signal is supplied. An input terminal, an output terminal that outputs an address signal to the terminal ADDl, an output terminal that inputs and outputs a data signal to the terminal DATl, an input/output terminal, and a terminal s'rBtrr.
This is an output terminal that outputs a data strobe signal (a pulse signal of "1" for a write command). Next, in CPU3. Terminal HLDrr is set to “1” only when the CPU 3 requests to prohibit access to the memory 5.
Terminal HLDArz, an input terminal to which a "1" signal is supplied; an output terminal that outputs a "1" signal when the "1" signal is supplied to the terminal HLDK and the cPU3 accepts or accepts this prohibition request;
Terminal ADD 2rx output Ruko that outputs the address signal;
Terminal DAT is an input/output terminal for inputting and outputting a 2σ data signal, and terminal 8TB2tfff is an output terminal for outputting an evening strobe signal. 172: Common memo 175VC, terminal ADD3r! These are an input terminal for inputting an address signal, a terminal for inputting and outputting a terminal DAT3rr data signal, and an input terminal for inputting all strobe signals of the terminal 8TB3σ data. Next, common memory controller 1m
, 3a, 18, 19, 20 are gates that are closed when a "1" signal is supplied to their input terminals E, 21, 22σ are gates that are closed when a "1" signal is supplied to their input terminals ! Bidirectional goo that becomes I), 23tf
If the address signal supplied from the f terminal ADDI indicates an address area allocated to the common memory 5, a
A "1" signal lfj is output from the output terminal C. ．． Also, when the input terminal 8K "1" signal is supplied, the terminal ADD1
The address signal supplied from terminal A I) D
This is a gate circuit that sends data to 3. 24 is reset at the rising edge of the "1" signal supplied to its input terminal RK. It is a flip roller 1 (hereinafter referred to as FF) that is set at the rising edge of the "1" signal supplied to the input terminal 8,
/fI is the output terminal on the set side of the output terminal Q, and 25 is an inverter. Next, the operation of the circuit shown in FIG. 2 will be explained. 1. In the initial state, the PF 24 is reset by a circuit (not shown). Here, the CPUI address signal -Jji output from the terminal ADD1 is rX if it does not indicate the address area of the common memory 5. Since the gate circuit 230 output Ruko C is outputting a "0" signal, the signal at the terminal HLD is a "0" signal. A "1" signal is supplied to the terminal RFIDY and the signal 61t is output, and a "0" signal is output from the terminal HLDA. Therefore, in this case, gate 1B, bidirectional gate 21 . Both gate lights of gate circuit 23 are closed. Since the gates 19, 20 and both gates 22 are open, the CPU 3 can access the common memory 5. Next, at present, the Tameda yard in Figure 3 is hidden, and at the time t.
In , when the address signal of the CPU 1 output from the terminal ADD1 indicates the address area of the common memory 5 (corresponding to the oblique @ part in the waveform H1 in FIG. 3), the terminal C of the gate circuit 23 becomes "1". Since the signal tube outputs, C
The signal at the terminal b of PU3 becomes a "1" signal (see (b) in Figure 3), and the 12-2FF24 is reset, so a "0" signal is supplied to the terminal REDYK of the CPU1 (
(see Figure 3 σ1G-1), as a result, the CPU 3 that has access to the CPUxa common memory 5 is rtn and v.
r is in a state where access to the common memory 6 is requested to be prohibited.
ib. Next, when the CPU 3 accepts the access prohibition request to the common memory 5 at time t, "l" is sent from the terminal HLDA.
”A signal is output from b (l [see G=111 in Figure 3),
FP24 is set and the signal supplied to the terminal plate is 1.
', r (along with h, the gates of gate 18, bidirectional gate 21, and gate circuit #23 are all open at t, and when C, the output of inverter 25 becomes a "0" signal, so gates 19 and 20° Both gates 22 are all in the closed state vcrx.As a result, the CPU 1ff is in a state where it is possible to write data to the common memory 5 and read data from the same common memory 5.
11. - rc is in a state where access to the 10,000 CPU 3σ common system 5 is prohibited; b, cPUlta here. Data is written to the common memory 5 or data is read from the σ common memory 5. 1! at time t in %A
, when the CPUI completes accessing the common memory 5, the signal output from the terminal C of the gate circuit 23 becomes the "0# signal" and the signal at the terminal HLD of the CPUI becomes "0".
” signal, the request to prohibit access to the common memory 5 for the CPU 3 is canceled.Next, at time t4VC, the CPU: lj accepts the cancellation of this prohibition request and outputs the terminal H.
The LDA signal t is returned to the "0" signal. This result CP
At U1' and 3, both become in the same state as before the clock. For one of these, if the configuration shown in Fig. 2 is constructed, the common memory 1J5t for CPU1 and CPU3 will not interfere with each other's operation, and can be used as if it were a dedicated memory. . Next, the overall operation of the process control system shown in FIG. 1 will be explained. The CPUI σ follows the program stored in the memory 2 (a program created using a normal programming language). Printing on the glitter 12, display on the CRT 13,
σ) Information exchange with host computer 14, digital input/output device 10? Input/output of digital signals used for purposes other than sequence control via analog input/output device 11? Line 7k') Performs input/output of anarch signals used for purposes other than sequence control through the %A line 7k') , - million c PU 3 r
iJ%4vr-stored%/%byagrams (10grams created using a sequence control language) according to the digital input/output device 16. ...The sequence control in this process control system is only 7 lines through the manufactured analog input/output device 117゜..., and in this case, from the CPU1tICPU3 to the common memory 5? Must go through it! ! information can be read from the CPU 3 to the common memory 5? Intervention 1. You can load the necessary information using According to this example, the calculation and control unit is used%/%
The 7t70 process control system can be constructed using a program written in one of the usual programming languages. A program created using a sequence control language and the operation of each other's central processing units. can be executed in parallel without any hindrance, and the entire machining process can be controlled. As explained above, the present invention includes a computer control device lamp,
First programming language? Created using -9 program? a first central processing unit that executes; This first central processing unit & common memory all valves 1. A second programming language that is connected to the first programming language and has a different σ type from the first programming language? A second central processing unit that executes a friend program created using ? Since they are set up, are there different types of program words IF? Multiple programs created using? It is possible to run % lines in parallel without interfering with the operation of each other's central processing units.Is this a program created using VCL, a high-level programming language that is difficult to understand, or a simple programming language? Since the 10 grams produced using the 10 grams can be completely separated, the creation and maintenance of programs becomes extremely easy. ! An extremely fast-responsive arithmetic and control unit? It can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing nine configuration examples in which one embodiment of the present invention is applied to a process control system, and Fig. 2 shows details of the arithmetic and control device in the same embodiment. FIG. 3 is a time chart for explaining the same embodiment. 1...First central processing unit, 1a...1 common memory controller output Shinko Electric Co., Ltd.

Claims (1)

[Claims] a first central processing unit that operates according to a program created using a first programming language; A second program that operates according to a program created using a second programming language different from
The central processing unit has a 1m/1m central processing unit with features and arithmetic and control equipment.