JPS61231654A - Memory device - Google Patents

Abstract

PURPOSE:To prevent drop in processing ability by dividing a memory device into plural banks, and providing a bus exclusively used for a processor and a circuit controlling access competition from a common bus at every bank. CONSTITUTION:The memory device 5-1 of a processor 3 is divided into three banks 12-14, which are connected to a competition control circuit (9-11). When the processor 3 indicates a processor 2 to transfer data in an external memory device 1 to an address allocated to the bank 12, the processor 2 transfers the data to the bank 12. On the other hand, when the processor 3 reads an instruction out of the bank 12 and executes such a program as writing data in the bank 14, processing can be executed without competing the data transfer action of the processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device in an information processing device configured by a plurality of processors.

[Conventional technology]

In a conventional multiprocessor system, a plurality of processors are connected to one common bus, and communication between the processors is generally performed via a storage device connected to the common bus. Furthermore, in the method that uses a common bus, the storage device is connected via a contention circuit to the internal bus of the processor that uses the storage device frequently and to the common bus, eliminating the overhead caused by bus contention for the processor. I am trying to improve my abilities. Figure 82 shows an example of the conventional system.

In the figure, the processors 2.3 are connected to one common bus 6, and the storage device 5 of the processor 3 is connected to the processor 3 through one contention control circuit 4, and the other through a dedicated bus 7. And the other one is also directly connected to the common path 6.

Processor 3 program.

The RAM is stored in the storage device 5. Processor 3 constantly accesses storage device 5 to read instructions.

Processor 3 now sends data from processor 2's external storage device 1 to processor 2 via common path 6 to storage device 5.
Consider the case where an instruction is given to forward the data to a predetermined address. Processor 2 begins transferring data onto storage device 5 according to the instructions.

[Problems to be solved]

However, the processor 3 always accesses the storage device 5.

Therefore, each access competes with the access of processor 2, resulting in a problem in that the processing performance of both processors 3 and 2 is reduced.

Solution to Problem c] The present invention solves the above problem.In a data processing device configured in which a plurality of processors having dedicated paths are connected to one common bus, In a storage device that can be accessed by a processor via a dedicated path and accessed by a processor other than the processor via a common path, the storage device is divided into a plurality of banks,
A dedicated bus for the processor and a circuit for controlling access contention from the common bus are provided for each bank,
It is a bad idea to have a configuration in which the processor accesses the storage device and the processor other than the processor accesses the storage device at the same time.

〔Example〕.

Next, an embodiment thereof will be explained with reference to FIG.

FIG. 1 is a block diagram of a multiprocessor system to which an embodiment of the storage device according to the present invention is applied;
The same parts as in FIG. 2 are given the same reference numerals.

In FIG. 1, a processor 3 and a processor 2 are connected to one common bus 6, an external storage device l is connected to the processor 2, and a storage device w5-1 of the processor 3 has three banks 12, 13. .14, and each of them is connected to a competition control circuit 4-4 (9,, 1·0°11)K.

Also, each competition control circuit 9. 1 and 0.degree. 11, one of which is connected to the internal valve of the processor 3 via a dedicated path 7-1, and the other connected to the common bus 6. Bank 12 includes processor 3. , is stored and displayed. ,1
．． ,... ・Processor 3 now says to processor 2,
The data of the processor 2Q external storage device 1 is applied to the bank 12 in the storage device 5-1 via the common path 6, and et al.
Consider the case where you instruct/direct to forward to an address that is Processor 2 transfers data to a predetermined address in bank 12 according to the instructions. Prosets on the other hand? 3, when executing a program that reads and writes instructions from banks 1 and 2 and writes data to bank 14, processing is performed without conflicting with the data transfer operation of processor 2. , by executing *, i, subordinate, point i, processor 3, 2 .・
In both cases, it is possible to reduce the decrease in processing capacity due to competition.

〔Effect of the invention〕

As explained above, the present invention divides a storage device into a plurality of banks, and each bank has a contention control circuit 5 and is connected to a dedicated processor path and a common bus of the system. This has the effect of reducing contention when accessing a device and reducing a decrease in processor processing performance. .゛

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system to which an embodiment of the storage device according to the present invention is applied, and FIG. 2 is a block diagram of a multiprocessor system to which a conventional storage device is applied.

Claims (1)

[Claims] In a data processing device configured such that a plurality of processors each having a dedicated bus are connected to one common bus, access by a specific processor via the dedicated bus and access from processors other than the common bus to the common bus is possible. In a storage device that can be accessed via A storage device characterized in that the storage device is configured such that the processor accesses the storage device and the processor other than the processor accesses the storage device at the same time.