JPS635461A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To lighten the competition relating to the use of a system bus and to improve a processing speed by transferring a program required for respective processors to an individual instruction storing memory from a common memory, fetching this instruction and processing. CONSTITUTION:At the time of the rise of a system, one of the processors PU21-2n reads the load instruction of the program from a ROM6 through the system bus 1. The PU21 loads the program in a magnetic disk 10 via a disk controller 7 and the program from a communication line 12 via a controller 9 in the common memory 3. At the time of the completion of this load, the program required for the processing assigned to itself is transferred to the instruction storing memory 41 from the memory 3. After the completion of the transfer, according to the instruction fetched from the memory 41 and by using a data area in the memory 3, the processing assigned to itself is performed. The PU22-2n similarly carries out the processing. Accordingly, the respective PUs make access to the memory 3 through the bus 1 only at the time of the access of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention Industrial Field of Application The present invention relates to a multiprocessor system used in various information processing systems.

Conventional technical information processing systems often employ a multiprocessor system configuration in which a plurality of processors and a common memory are connected via a system bus, and each processor is configured to perform function distribution and load distribution processing.

In this type of multiprocessor system, a program storage area for storing programs for each processor and a data buffer area for storing data being processed are provided on a common memory.

Problems to be Solved by the Invention In the conventional multiprocessor system described above, each processor reads instructions one by one from a common memory via a system bus, so as the number of processors increases, the demand for use of the system bus increases. There is a problem in that the contentions compete with each other, prolonging the waiting time for reading instructions and reading/writing data, and reducing processing speed.

In particular, recently, advanced fetching of instructions has been performed, but if the data read waiting time is prolonged, the advanced fetching instruction cannot be executed immediately, and the advantage of advance fetching is lost.

Means for Solving the Problems of the Structure of the Invention The multiprocessor system of the present invention which solves the problems of the prior art described above has an instruction storage memory installed in all or part of the processors, and one of the processors At this time, the programs used by each processor in this system are loaded into a common memory, and the processors equipped with instruction storage memory transfer necessary programs from the common memory into their own instruction storage memory. The system bus is configured so that the system bus is used only for data access by storing the instructions and thereafter fetching and processing instructions from the own instruction storage memory.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of a multiprocessor system according to an embodiment of the present invention.

This multiprocessor system includes a system bus 1 and a plurality of processors 2 . ．． 2□ ...2. , and a common memory 3 connected to the system bus 1 and accessed by each of the processors 21-21. Processor 21~
2. , each of , is an instruction storage memory, j, , 4
□ ...4.1 and individual buses 51, 5□ ...57
It is equipped with Furthermore, this multiprocessor system includes a ROM 6, a disk controller 7, a terminal controller 8, a line controller 9, a magnetic disk 10 . A terminal device 11 is also provided.

When starting up this multiprocessor system, one of the processors 21 to 2fi (here, processor 2.
) reads a program load instruction from the ROM 6 via the system bus l.

In accordance with this load instruction, the processor 21 loads the program in the magnetic disk 10 via the disk controller 7 or the program transferred from a higher-level device onto the communication line 12 via the line controller 9 into the common memory 3. Load into program storage area.

When the loading of the program to the common memory 3 is completed, the processor 2I transfers the program necessary for the process assigned to it from the common memory 3 to the instruction storage memory 4. Transfer to. When the transfer is completed, the processor 21 executes the instructions fetched from the instruction storage memory 4I.
And, it uses the data area in the common memory 3 to perform the processing assigned to itself. Similarly, the other processors 2□-2, 1 first transfer the programs necessary for the processes assigned to them from the common memory 3 to the instruction storage memories 42-41. When this transfer is completed, processors 2□ to 2n
This memory for storing instructions 4□-4. , and using the data area in the common memory 3, starts the process assigned to it.

Therefore, each processor accesses the common memory 3 via the system bus 1 only when accessing data.

The above example shows a configuration in which instruction storage memory is installed in all processors in the system, but for some types of processors whose system bus is infrequently used, instruction storage memory is not installed and common memory is used as usual. It may also be configured to allow access.

Effects of the Invention As explained in detail above, in the multiprocessor system of the present invention, each processor transfers a program necessary for processing from a common memory to an individual instruction storage memory, and performs processing by fetching the instructions. Because of this configuration, accesses to the common memory are limited to data-related accesses, which greatly alleviates contention regarding the use of the system bus and significantly improves processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a multiprocessor system according to an embodiment of the present invention. 1. System bus, 2. ~211...processor,
4. Processor 2. Common memory accessed by ~2n, 41-4, . . . Instruction storage memory, 51-5.
l...Individual bus, 6...ROM, 7...disk control device, 8...line control device.

Claims (1)

[Scope of Claims] A system bus, a plurality of processors connected to the system bus, a common memory connected to the system bus and accessed by each processor, and a common memory connected to one of the processors via an individual bus. a plurality of instruction storage memories, one of the processors loads a program used by each processor in the system into the common memory when starting up the system; A multiprocessor characterized in that it transfers necessary programs loaded into memory from this common memory to its own instruction storage memory, and performs subsequent processing by fetching instructions in its own instruction storage memory. ·system.