JPS6326744A - Memory bank switching circuit for microprocessor - Google Patents

Abstract

PURPOSE:To switch memory banks at high speed by providing an instruction code detecting means separately from a central arithmetic processor to detect a specific instruction code which designates the switch of memory banks. CONSTITUTION:The data on an FF is read to a CPU 2 and a memory fetch signal is kept active. In such a case, the FF data is detected by a coincidence circuit 14 and the FF is set. As a result, a memory bank 4 is switched to a memory bank 6. Hereafter the data corresponding to the addresses designated by the CPU 2 are read out of the bank 6. When those data read out successively out of the bank 6 are equal to 01 at a time point, the bank 6 is switched to the bank 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory bank switching circuit used to expand memory capacity in a microprocessor.

(Prior Art) The memory capacity that can be used by a microprocessor is basically determined by the size of the address bus of the microprocessor. For example, if there are 16 address buses, the memory capacity that can be used by the microprocessor is approximately 64.
bytes (21″=65°536 bytes). Also, if there are 20 address buses, the memory capacity is approximately I M
bytes (2” = 1°048, 576 bits).Despite the basic limitation of memory capacity due to the size of the address bus, in order to further expand the memory capacity, a memory bank switching method has been developed. It has been considered for a long time.

This memory bank switching method is based on the central processing
A plurality of memory banks are arranged on a common address bus from PU), and a desired memory bank can be selected and accessed from among these memory banks. A conventional memory bank switching circuit will be explained below with reference to FIG.

A plurality of (two in FIG. 2) memory banks 4.6 are arranged on a common address bus A and a common data bus B from the CPU 2, each having a common address group within an accessible range. ing. In order to switch the memory bank 4.6, the memory bank switching circuit connects the first decoder 8 connected to the input/output port of the CPU 2.
, a second decoder 10 connected to the first decoder 8 and the data bus B of the CPU 2, and a latch circuit 12 connected to the second decoder 10.

The reason why such a memory bank switching circuit is required is as follows. For example, when CPtJ2 accesses address 100, since the same address 100 exists in each of the plurality of memory banks 4 and 6, if the address 100 is not specified in which memory bank, an incorrect memory will be accessed. This is because troubles such as data being written to a bank or data read from each memory bank colliding with each other may occur.

Next, the memory bank switching operation of the conventional example shown in FIG. 2 will be explained.

First, when the first decoder 8 receives a memory bank switching command signal from the input/output port of the CPU 2, the first decoder 8 selects a port for switching the memory bank 4.6 and sends a signal to the second decoder 10. Activate it by issuing the . In this state, the second decoder 1
When a memory bank designation signal specifying, for example, memory pan chromatization is input from the CPU 2 to 0 via the data bus B, the second decoder 10 outputs a memory bank selection signal corresponding to the memory bank designation signal to the launch circuit 12. . As a result, the launch circuit 12 outputs a signal that enables only the memory panchromator corresponding to the memory bank selection signal, and thereafter maintains this state until a new memory bank selection signal is applied. Therefore, if an address is accessed from CPIJ2 via address bus A during this time, reading and writing will be performed only for the memory panchrome selected at this time.

However, in the conventional memory bank switching circuit as described above, each time the bank is switched, the CPU 2
Since bank information must be set in the input/output port of the memory before accessing the memory, it takes a considerable amount of time to switch banks. Therefore, there is a problem in that the efficiency of the system decreases as the number of times memory banks are switched increases.

(Object of the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to switch memory banks at high speed.

(Structure of the Invention) In order to achieve the above object, the present invention adopts the following +i configuration.

That is, the present invention provides a memory bank switching circuit that selects a desired memory bank from a plurality of memory banks arranged on the address bus of a central processing unit (CPU), and Separately from the central 64 arithmetic processor, an instruction code detecting means for detecting a specific instruction code specifying switching of memory banks from data is provided, and based on the output of the instruction code detecting means, the plurality of memory banks are detected. The present invention is characterized in that a memory bank corresponding to the specific instruction code is selected from among the memory banks.

Next, the above-mentioned invention will be explained in detail.

A specific instruction code specifying memory bank switching from a certain memory bank is detected by an instruction code detection means provided separately from the CPU, and the memory bank is switched based on the output of this detection means.
Memory banks can be switched at high speed compared to the conventional example in which memory banks are switched after once an instruction code is loaded into the CPU and bank information is set in the CPU's human output port.

(Embodiment) FIG. 1 is a block diagram of a memory bank switching circuit in a microprocessor according to one embodiment of the present invention. In this figure, the same parts as in FIG. 2 are designated by the same reference numerals. The memory bank switching circuit, which is the main part of this embodiment, consists of two one-failure circuits 14 connected to data bus B.
．． 16, AND gates Gl and G2 which are respectively supplied with the outputs of these negative circuits 14 and 16, and the AND gates G1. It consists of a flip-flop FF etc. to which each output of G2 is applied as a set/reset input. And match circuit 14.16 and antgame)G
1 and G2 correspond to the instruction code detection means described in the section of the configuration of the invention, as will become clear from the explanation to be given later. The operation of this embodiment will be explained below.

The matching circuit 14 is preset to become active when, for example, a code 'FFJ' appears on the data bus. Furthermore, the -defeat circuit 16 is set to become active when, for example, a code "01" appears. Here, the instruction code 'FFJ is data for selecting one size of memory panchromatic, and is written to a predetermined address of the memory bank 4. Instruction code “0”
1'' is data for selecting the memory bank 4, and is written at a predetermined address in the memory panchromatic memory.

Assume that memory bank 4 is currently being accessed. When executing a program, the CPU 2 calls instructions from a memory bank. Memory Bank 4
is being accessed, the data in the memory bank 4 is sequentially read into the CPU 2 and processed. In such a data read procedure, first, a memory address is specified on the address bus A, and data is read from the location corresponding to the address, and is taken into the CPU 2 through the data bus B.

On the other hand, the CPU 2 receives a control signal (memory fetch signal) indicating whether the data read from the data bus B is an instruction code for the CPU 2 or basic data.
is output at a predetermined timing. For example, the memory fetch signal goes to the rHJ level when the read data is an instruction code, and goes to the 'LJ level when the read data is just data. Now CPU2
Assume that the data read in is 'FFJ' and the memory fetch signal is in an active period ('HJ level) at this time. Then, in the matching circuit 14, the data r
FFJ is detected and its detection signal is sent to the AND gate Gl.
The flip-flop FF is set by being applied to the flip-flop FF via the FF. the result,
Flip-flop FF for memory panchromatic control Lt child C
The rH and level outputs of the memory bank 4 are switched from the memory bank 4 to the memory panchromatic mode by providing the 'LJ level outputs inverted by the inverter G3 to the control 4H52 child C of the memory bank 4.

Thereafter, data corresponding to the address specified by the CPU 2 is read from the memory panchromatic memory and processed by the CPU 2.

Assume that the next data read out from the memory panchromatic recorder becomes 'OIJ' at a certain point in time, and the memory fetch signal is active at that time.

Then, the output signal of the 1jkffl path 16 that detected the data "01" is applied to the flip-flop FF via the AND gate G2. The flip-flop FF is reset by this signal. As a result, the memory bank 4
The control terminal C of the memory panchromat becomes 'HJ level, the control terminal C of the memory panchromatic becomes 'LJ level, and the memory panchromatic is switched to memory bank 4.

In the above embodiment, a microprocessor equipped with two memory banks has been described as an example, but the present invention is not limited to this, and an arbitrary number of memory banks can be provided. be. And in this case,
Of course, an instruction code detection means such as the matching circuit described in the above embodiment is provided corresponding to each memory bank.

(Effects of the Invention) As is clear from the above description, the memory bank switching circuit according to the present invention uses a specific instruction code output from the memory bank onto the data bus to designate the memory bank switching. The instruction code is detected by an instruction code detection means provided separately from the CPU, and memory banks are switched based on the output of this detection means.

Therefore, according to the present invention, the instruction code is once sent to the CPU.
Memory banks can be switched at high speed compared to the conventional example in which bank information is read into the input/output port of the CPU, and memory banks are switched via a decoder.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory bank switching circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional memory bank switching circuit. 2...CPU, 4.6...Memory bank, 14.1
6...-Several circuits, G1. G2...and gate, F
F...Flip-flop

Claims (1)

[Claims] A memory bank switching circuit in a microprocessor that selects a desired memory bank from a plurality of memory banks arranged on an address bus of a central processing unit (CPU), the circuit selecting a desired memory bank from among data read from the memory bank. Instruction code detection means for detecting a specific instruction code specifying switching of memory banks is provided separately from the central processing unit, and based on the output of the instruction code detection means, the specified instruction code is selected from among the plurality of memory banks. A memory bank switching circuit in a microprocessor, characterized in that it selects a memory bank corresponding to an instruction code.