JPS5835295B2 - Data transfer method in master-slave system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method in a masked slave system.

A mask central processing unit (referred to as a master CPU) equipped with a main memory, and a plurality of slave central processing units (slave CPUs) controlled by this master CPU and each having an internal memory.
A masked slave system is well known in which input/output devices are controlled by a slave CPU.

In some devices, data transfer between the main memory and the internal memory is performed by a slave CPU.

In such a mask slave system, the mask CPU cannot directly access the internal memory of the slave CPU.

To enable the master CPU to access the slave CPU's internal memory, a separate data bus,
It is conceivable to provide an address bus, a control circuit, etc.

However, if this is done, the wiring of the data bus and address bus becomes complicated, and data transfers based on the control of the slave CPU and data transfers based on the control of the master CPU coexist, and the main memory and internal The control circuit for data transfer to and from the memory also becomes complex.

This invention allows the master CPU to connect to the slave CPU without providing an extra data bus or address bus.
The present invention provides a data transfer method in a mask slave system in which data transfer between the main memory and the internal memory is controlled by accessing the internal memory of the main memory.

The present invention will be described in detail below with reference to the drawings.

In Figure 1, a master CPU that controls the entire system
21 is connected to a plurality of slave CPUs 31 by a bus 40 including a data bus, a control bus, and an address bus.

In this example, two slave CPUs 31 are shown for convenience, but an appropriate number of slave CPUs 31 may be provided as needed.

When distinguishing between two slave CPUs, each
1A and 31B.

Each slave CPU 31 controls a dedicated input/output device 37.

The master CPU 21 includes a main memory 22, this main memory 22
The master CPU 21 includes a DMA control circuit 23 for controlling reading and writing from or to the main memory 22 by the slave CPU 31, an input/output command control circuit 24 for the master CPU 21, and an interrupt control circuit 25.

Each slave CPU 31 includes an internal memory 32, a data transfer control circuit 33 that communicates with a DMA control circuit 23 to exchange data with the main memory 22, an input/output command control circuit 34, an interrupt generation circuit 35, and a dedicated An input/output control circuit 36 for each input/output device 37 is provided.

As shown in FIG. 2, the main memory 22 and internal memory 32 function as a data memory for storing various data, and as a program memory for storing execution programs of the master CPU 21 and slave CPU 31, respectively. Each is composed of parts.

The data memory of the main memory 22 has an area M1 in which an instruction code to be read by the slave CPU 31 is set after starting the slave CPU 31 as described later.
is provided, and the program memory contains slave CPU3.
There are provided an area M2 where an execution program of the slave CPU 31 to be transferred to the internal memory 32 of No. 1 is stored, and an area M3 where a program transferred from the internal memory 32 is stored.

The program memory of the internal memory 32 includes an area M4 that stores a program that controls the data transfer control circuit 33 and performs data transfer, an area M5 that stores a program read from area M2 of the main memory 22, and an area M5 that stores a program read from the area M2 of the main memory 22. An area M6 is provided in which a program to be transferred to the area M3 is stored.

These Elijah M2. M3. M5. Needless to say, M6 is not limited to one location, and may be provided at an appropriate number of locations over an appropriate address range.

Further, the address range may be fixed or may be specified each time.

The instruction code sent from the master CPU 21 to the slave CPU 31 is the instruction content and DMA information shown in FIG.

The DMA information includes the start address of the area (in this example, area M2 or M3) involved in data transfer in the main memory 22, the start address of the area (M5 or M6) involved in data transfer in the internal memory 32, and the transfer word. (
consists of a number of bytes).

The command contents shown in FIG. 3 include a write command to transfer the contents of area M6 of the internal memory 32 to area M3 of the main memory 22, and a write command to transfer the contents of area M2 of the main memory 22 to area M5 of the internal memory 32. A read command for transferring, a jump command indicating that after reading the program of Area M2 to Area M5, a jump is to be made from the DMA program of Area M4 to the read program, and an S-CPU specifying the slave CPU 31. It consists of an identification code.

Transfer of program data between the main memory 22 and the internal memory 32 is started by the slave CPU 31 under the control of the mask CPU 21.

Referring to FIGS. 4 and 5, the mask CPU 21 sets an instruction code in the area M1 of the main memory 22 (step 1), and in response to a program output command, a specific slave C
Activate the PU 31 (step 2).

The slave CPU 31 includes input/output command control circuits 24 and 34.
The master CPU 21
Recognize the program output command from (step 11)
.

As a result, the slave CPU 31 uses the free time when the master CPU 21 is not using the main memory 22 to
Data is transferred via the data transfer control circuit 33 and DMA control circuit 23, and the instruction code set in area M1 of the main memory 22 is fetched (step 12).

Then, it is checked whether the slave CPU identification code in the instruction code matches that indicating the slave CPU 31 (step 13).

and the slave CPU specified by the identification code.
31 executes the following processing except for the interrupt processing in step 20.

If the slave CPU identification codes match, the instruction code is checked to determine whether it is a write instruction (step 14) or a read instruction (step 16).

If it is a write command, the slave CPU 31 controls the data transfer control circuit 33 to communicate with the DMA control circuit 23, and transfers data from the internal memory specified by the DMA information during free time when the master CPU 21 is not using the main memory 22. 32 start address (area M6), the specified number of words of program data are read out in order from the main memory 2.
Data is transferred in order from the start address of area M3 (area M3) (step 15).

After the data transfer is completed, the slave CPU 31
21 to notify that the transfer process has ended (step 20).

In the case of a read command, the start address (area M2
), the specified number of words of program data are sequentially transferred from the start address (area M5) of the internal memory 32 (step 17).

Then, it is checked whether there is a jump instruction among the instructions in the instruction code (step 18), and if there is a jump instruction, the program jumps from the DMA program of Elijah M4 to the program of M5 and executes that program (step 19). ).

Thereafter, the master CPU 21 is notified by interrupt that all processing has been completed (step 20).

If there is no jump command, interrupt the master CPU 21 to notify that the transfer process has ended (step 2
0).

If it is confirmed in step 14.16 that it is neither a write command nor a read command, the process moves to step 20 and interrupts the mask CPU 21 without executing any processing.

If the slave CPU 31 detects that it is not designated by the slave CPU identification code (NO in step 13), the slave CPU 31 proceeds to step 20 and interrupts the master CPU 21 without executing any of the above-described processes.

Note that when a jump command is issued in step 18, an interrupt may be first issued (step 20), and then the program may be executed (step 19).

The master CPU 21 learns that the data transfer has ended due to an interrupt from the slave CPU 31 (step 3).
.

As a result, under the control of the master CPU 21, the slave CPU 31 performs data transfer between the internal memory 32 and the main memory 22 through direct memory access to the main memory 22 (
DMA).

In the above example, the program is the transfer data,
It goes without saying that other types of data can also be transferred between the main memory 22 and the internal memory 32.

As explained in detail above, according to the present invention, in a masked slave system in which the main memory can be directly accessed by the slave CPU, an instruction to instruct the main memory to access the internal memory of the slave CPU is provided. The contents are memorized and the slave CPU is the master CPU.
The main memory is accessed based on the loaded instruction, and data is transferred between the main memory and the internal memory.
There is no need to provide an extra data bus, address bus, etc., and the master CPU accesses the internal memory of the slave CPU to control data transfer between the main memory and the internal memory.

This allows the main memory of the master CPU and the slave CPU to
It is possible to transfer data between the internal memory of
It becomes possible for the master CPU to check the contents of the internal memory (eg, PROM) of the slave CPU.

Also, programs that are not in the internal memory of the slave CPU, such as a program for checking the slave CPU's hardware, an extension program for the slave CPU, etc., are read from the external storage device managed by the master CPU to the mask CPU, and then transferred to the slave CPU. be able to.

Then, when the master CPU gives a read jump command to the slave CPU, the slave CPU executes the program transferred to its internal memory, so the mask C
The PU can also perform hardware checks on slave CPUs.

[Brief Description of the Drawings] Figure 1 is a block diagram showing the overall configuration, Figure 2 is a diagram showing the contents of the main memory and internal memory, Figure 3 is a diagram showing the format of the instruction code, and Figure 4 is a diagram showing the contents of the main memory and internal memory. FIG. 5 is a flow chart showing the processing procedure of the mask CPU, and FIG. 5 is a flow chart showing the processing procedure of the slave CPU. 21...Mask central processing unit, 22...
・Main memory, 23...DMA control circuit, 31.
... Slave central processing unit, 32 ... Internal memory, 33 ... Data transfer control circuit.

Claims (1)

[Claims] 1 A mask consisting of a mask central processing unit having a main memory and a plurality of slave central processing units each having an internal memory and controlled by the mask central processing unit, the main memory being accessible by the slave central processing unit. - In the slave system, the main memory includes a first area in which an instruction code to be read by the slave central processing unit is set after starting the slave central processing unit, and a first area that is transferred to the internal memory of the slave central processing unit. a second area for storing data transferred from the internal memory; and a third area for storing data transferred from the internal memory, the internal memory storing data transferred from the second area of the main memory. There is a fourth area and a fifth area storing data to be transferred to the third area of the main memory, and the instruction code is
from the second area of the main memory to the fourth area of the internal memory.
a read command for instructing data transfer to an area of the internal memory, a write command for instructing data transfer from the fifth area of the internal memory to the third area of the main memory, and a write command for instructing data transfer from the fifth area of the internal memory to the third area of the main memory; the mask central processing unit; the mask central processing unit; sets a predetermined instruction code in the first area of the main memory, the slave central processing unit obtains the instruction code by activation from the mask central processing unit, and executes the master instruction code based on the obtained instruction code. accessing memory to perform data transfer between the main memory and the internal memory;
If the instruction code includes a read/jump instruction, the program jumps to the program read into the fourth area in the internal memory after the program/data transfer is completed, and executes the program. ,mask·
Data transfer method in slave system.