GB2121997A - Testing modular data processing systems - Google Patents

Testing modular data processing systems Download PDF

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Publication number
GB2121997A
GB2121997A GB8315751A GB8315751A GB2121997A GB 2121997 A GB2121997 A GB 2121997A GB 8315751 A GB8315751 A GB 8315751A GB 8315751 A GB8315751 A GB 8315751A GB 2121997 A GB2121997 A GB 2121997A
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Prior art keywords
shift register
control
paths
module
common input
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8315751A
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GB2121997B (en )
GB8315751D0 (en )
Inventor
Alan Spillar
Peter Leo Lawrence Desyllas
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Fujitsu Services Ltd
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Fujitsu Services Ltd
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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2294Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by remote test

Abstract

A data processing system is constructed from processing modules (e.g. LSI chips). Each module 11 contains storage circuits which are connected together, for test and diagnostic purposes, to form a plurality of shift register paths 12 in parallel between common input 15 and output 17 terminals. The common terminals on all the modules are connected to a diagnostic unit 13 by way of common input and output lines. In operation, a first control message from the diagnostic unit is shifted into a master shift register 21, connected to the common input line, and this causes one of the modules 11 to be selected. A second control message from the diagnostic unit is then shifted into a control shift register 23 in the selected module, and this causes one of the shift register paths 12 in that module to be selected. Test data can then be shifted into the selected path from the diagnostic unit. <IMAGE>

Description

SPECIFICATION Data processing system Background to the invention This invention relates to data processing systems. More specifically, the invention is concerned with arrangements for testing such systems.

One previously proposed arrangement for testing a data processing system is described in British Patent Specification No. 1,536,147. In that specification, the internal data storage circuits of the system are connected together to form a plurality of serial shift register paths. Normally, the paths are disabled, preventing them from being shifted. However, in a diagnostic mode of operation, a selected one of the paths is enabled, allowing its contents to be shifted. This permits test patterns to be shifted serially into the storage circuits of that path, and the contents of these circuits to be shifted out for inspection.

A data processing system is usually constructed from a number of modules such as large-scale integrated circuits (LSI) chips. It may be desirable for each module to contain several shift register paths as described above. However, a problem which arises in this case is that the number of pins or terminals on the module is limited and hence there may not be enough pins available for all the necessary connections to the paths, for selection, control and data input/output.

One object of the present invention is to alleviate this problem.

Summary of the invention According to the invention, there is provided a data processing module comprising a plurality of serial shift register paths, connected in parallel between common input and output terminals on the module, and selection means for selecting one of the paths to allow test data and results to be shifted serially through that path, the selection means comprising: (a) a control shift register connected to the common input terminal, (b) means for enabling the control shift register to receive a control message shifted serially into it from the common input terminal, the control message containing information identifying one of the paths, and (c) means responsive to the control message in the control shift register, for selecting the path identified by that message.

it can be seen that the common input terminal is used not only for shifting data into the paths, but also for receiving the control message which selects the required path for shifting. This results in a significant saving in the number of terminals required.

The control message may also contain a function code specifying a mode of operation for the paths or for the selected path.

One data processing system in accordance with the invention will now be described by way of example with reference to the accompanying drawings.

Brief description of the drawings Figure 1 is a block circuit diagram of the system.

Figure 2 illustrates a modification of the system.

Description of an embodiment of the invention General Referring to Figure 1, the data processing system comprises a plurality of printed circuit boards 10. Each board carries a plurality of largescale integrated circuit (LSI) chips 11. Each of these chips contains data storage circuits, such as bistables and registers, connected by combinational logic circuits such as logic gates and multiplexers, to form the processing circuits required for the normal processing operation of the system. These processing circuits, and the manner in which they are interconnected, form no part of the invention and so will not be described in detail herein.

As well as being interconnected to form the normal processing circuits, the data storage circuits are also connected together serially, for diagnostic and testing purposes, to form four shift register paths 12 in each chip. Typically, each path may contain up to 72 individual bits. Normally, all the paths in all the chips are inhibited, preventing their contents from being shifted. In this condition, the data storage circuits perform their normal processing functions. However, in a diagnostic mode of operation, one path is selected and enabled for shifting. This permits test patterns to be shifted into the storage circuits of the selected path, and the contents of the selected path to be read out serially.

The system also contains a diagnostic unit 13 which controls the selection of the paths, generates the test patterns, and receives the contents of the paths for inspection. The diagnostic unit 13 produces a serial data input signal LDI on line 14, which is distributed to all the boards 10 and is fed to a serial input terminal 15 on each chip 11. The terminal 15 is connected in parallel to the inputs of all the paths 12 on the chip.

The outputs of the paths are connected to a multiplexer 16 which selects one of the outputs and feeds it to a serial output terminal 17 by way of a multiplexer 18, when a control signal GO = 1.

(The signal GO is supplied to all the chips.) The output terminal 17 is connected to a multiplexer 1 9 with similar outputs from the other chips on the board. The output of the multiplexer 19 is connected to another multiplexer 20 with similar outputs from the other boards, to produce a serial data output signal LDO which is returned to the diagnostic unit 13.

Each board contains a shift register 21 referred to as the master shift register. Normally this register is disabled, preventing its contents from shifting. The register 21 is enabled by a board select signal BSEL from the diagnostic unit. When enabled, it has a message shifted into it, one bit at a time, from the line 14, under control of a clock signal CLK. (This clock signal is also received by all the chips 1 1). Data is also shifted out of the register 21 and returned to the diagnostic unit by way of the multiplexer 19.

The message shifted into the master shift register 21 contains a chip select code, identifying one of the chips 11. This is decoded by a decoder circuit 22 to produce a chip select signal CSEL for the specified chip. One value of the chip select code serves as a broadcast code, and causes all the outputs of the decoder 22 to be enabled, sending chip select signals CSEL to all the chips simultaneously.

Each chip contains a shift register 23 referred to as the control shift register. Normally this register is disabled. The register 23 is enabled by the AND function of the chip select signal CSEL and the inverse of the control signal GO. When enabled, the register 23 has a message shifted into it, one bit at a time, from the terminal 15, under control of the clock CLK. Data is also shifted out of the register and returned to the diagnostic unit by way of the multiplexer 18, when GO=O.

The message shifted into the control shift register 23 includes path select code specifying one of the four paths 12 on the chip. This code controls the multiplexer 16 so as to select the output of the specified path. The code is also decoded by a decoder circuit 24 to produce a path selection signal LSEL for the specified path.

The message also contains a loop function code which specifies a desired mode of operation for the paths. This is decoded by a decoder circuit 25 to produce function control signal FN for the paths. The first three of the function control signals have the following meanings: RUN: All the paths inthe chip are put into a normal RUN mode of operation in which all the data storage circuits on the chip perform their normal processing functions.

HOLD: All the paths on the chip are put into a hold mode in which their contents are frozen, preventing them from being overwritten.

SHIFT: One of the paths, specified by the path select signal LSEL, is placed in a SHIFT mode in which its contents are shifted from left to right as viewed in Figure 1, one step at each clock pulse.

At the same time the other three paths on the chip are put into the HOLD mode.

The function control signals are valid only if GO = 1; when GO = O all the paths on the chip are frozen.

Operation It is assumed that initially the control shift register 23 in each chip contains the RUN function code and that GO = 1, so that all the processing circuits are running normally.

(a) First, the GO signal is removed. This temporarily freezes the operation of the processing circuits.

(b) A board selection signal BSEL is then applied to one or more of the boards, enabling the master shift register 21 in the (or each) board.

(c) A message is now shifted into the master shift register 21 of the selected board, over the line 14. This selects one chip on the board (or, in the case of the broadcast code, selects all the chips on the board).

(d) The signal BSEL is now removed, preventing any further data from being shifted into the master shift register.

(e) A message is now shifted into the control shift register 23 of the (or each) selected chip, over the line 14. This causes the required path to be selected, and generates the function control signals for the paths.

(f) The GO signal is restored.

For example, the above procedure may be used in the following manner.

(a) Using the broadcast code, all the paths in the system are set into the HOLD mode.

(b) One selected path is then set into the SHIFT mode, allowing its contents to be shifted out to the diagnostic unit 13 for inspection, and allowing tests patterns to be shifted into it from the diagnostic unit.

(c) Finally, the broadcast code is used again to restore all the paths to the RUN mode.

In summary, it can be seen that an individual path is selected by a three stage process. First, a board is selected, then one chip on that board, and then one path within that chip. The chip and the path are selected by messages sent by the diagnostic unit 13 serially over the line 14. Each chip 1 1 requires only a single input terminal 1 5 for receiving these messages, and this same terminal is also used for receiving input data for the paths 12.

A possible modification In the system described above, the decoder 22 has a separate chip selection line CSEL for each chip 11. Thus, for example, a group of ten chips will require ten such lines. This may be a problem if there are not enough output pins available on the decoder 22, which may itself be a LSl chip.

Referring to Figure 2, in a modification of the system described above, one out of a group of ten chips is selected by a set of five selection lines 30 leading from the decoder 22. These lines carry a two-out-of-five code which identifies one of the chips as follows: Chip No. Code 0 10001 1 10010 2 2 10100 3 11000 Chip No. Code 4 01001 5 01010 6 01100 7 00101 8 00110 9 00011 As shown, each chip has two selection terminals 31, 32 which are connected to the two lines 30 corresponding to the two ones in the code for that chip. For example, the terminals 31, 32 on chip No. 0 are connected to the first and last of the lines 30. The signals from the terminals 31,32 are combined in an AND gate 33 on the chip, to produce the chip select signal CSEL for that chip.

It can be seen that whenever one of the above codes is applied to the lines 30, only one of the chips will have both its terminals 31,32 activated, and only that chip will be selected. The decoder 22 deals with the broadcast code mentioned above by activating all the lines 30, so as to select all the chips.

In the modification described above, the use of the two-out-of-five code reduces the number of outputs from the decoder 22 from ten to five. Each chip 11 now requires an extra terminal since it receives two selection input signals instead of one A similar coding arrangement may be used for selecting the boards 10, so as to reduce the number of board select lines BSEL from the diagnostic unit 13.

Claims (8)

1. A data processing module comprising a plurality of serial shift register paths, connected in parallel between common input and outer terminals on the module, and selection means for selecting one of the paths to allow test data and results to be shifted serially through that path, the selection means comprising: (a) a control shift register connected to the common input terminal, (b) means for enabling the control shift register to receive a control message shifted serially into it from the common input terminal, the control message containing information identifying one of the paths, and (c) means responsive to the control message in the control shift register, for selecting the path identified by that message.
2. A module according to Claim 1 wherein said module is an integrated circuit chip.
3. A module according to Claim 1 or 2 wherein the control message also contains a function code for controlling the mode of operation of the paths, or the selected path, within the module.
4. A module according to any preceding claim in combination with a diagnostic unit connected to the input and output terminals and arranged to generate said control messages and test data.
5. A data processing system comprising a plurality of modules according to Claims 1,2 or 3 wherein the common input terminals of all the modules are connected to a common input line.
6. A system according to Claim 5 further including a control unit for selecting one of the modules, the control unit comprising: (a) a master shift register connected to the common input line, (b) means for enabling the master shift register to receive a control message shifted serially into it from the common input line, the control message containing information identifying one of the modules, and (c) means responsive to the message in the master control shift register for selecting the module identified by that message.
7. A system according to Claim 6 wherein the control unit selects the modules by means of an nout-of-m code.
8. A data processing system having means for selecting serial shift register paths substantially as hereinbefore described with reference to the accompanying drawings.
GB8315751A 1982-06-11 1983-06-08 Testing modular data processing systems Expired GB2121997B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB8217006 1982-06-11
GB8315751A GB2121997B (en) 1982-06-11 1983-06-08 Testing modular data processing systems

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Application Number Priority Date Filing Date Title
GB8315751A GB2121997B (en) 1982-06-11 1983-06-08 Testing modular data processing systems

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GB8315751D0 GB8315751D0 (en) 1983-07-13
GB2121997A true true GB2121997A (en) 1984-01-04
GB2121997B GB2121997B (en) 1985-10-09

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209982A2 (en) * 1985-07-25 1987-01-28 International Computers Limited Digital integrated circuits
EP0210741A2 (en) * 1985-07-25 1987-02-04 International Computers Limited Digital integrated circuits
US4764926A (en) * 1984-12-21 1988-08-16 Plessey Overseas Limited Integrated circuits
US4780628A (en) * 1986-11-06 1988-10-25 International Computers Limited Testing programmable logic arrays
US4780627A (en) * 1986-11-06 1988-10-25 International Computers Limited Testing programmable logic arrays
EP0388001A2 (en) * 1989-02-10 1990-09-19 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Testing method and apparatus for an integrated circuit
WO1993002415A1 (en) * 1991-07-25 1993-02-04 Siemens Aktiengesellschaft Device for testing electronic components of a unit interconnected according to the application
WO1993006497A1 (en) * 1991-09-23 1993-04-01 Digital Equipment Corporation Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip
GB2388199A (en) * 2002-04-30 2003-11-05 Samsung Electronics Co Ltd Multiple scan chains with pin sharing
DE10241385A1 (en) * 2002-09-06 2004-03-25 Infineon Technologies Ag Integrated circuit for mobile radio equipment having function blocks with individual control systems
GB2399890A (en) * 2002-04-30 2004-09-29 Samsung Electronics Co Ltd Multiple scan chains with output pin sharing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1536147A (en) * 1975-07-02 1978-12-20 Int Computers Ltd Data processing systems
GB2029612A (en) * 1978-05-09 1980-03-19 Hitachi Ltd Data buffer control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1536147A (en) * 1975-07-02 1978-12-20 Int Computers Ltd Data processing systems
GB2029612A (en) * 1978-05-09 1980-03-19 Hitachi Ltd Data buffer control system

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764926A (en) * 1984-12-21 1988-08-16 Plessey Overseas Limited Integrated circuits
EP0209982A2 (en) * 1985-07-25 1987-01-28 International Computers Limited Digital integrated circuits
EP0210741A2 (en) * 1985-07-25 1987-02-04 International Computers Limited Digital integrated circuits
US4730316A (en) * 1985-07-25 1988-03-08 International Computers Limited Digital integrated circuits
EP0210741A3 (en) * 1985-07-25 1989-03-01 International Computers Limited Digital integrated circuits
EP0209982A3 (en) * 1985-07-25 1989-03-08 International Computers Limited Digital integrated circuits
US4780628A (en) * 1986-11-06 1988-10-25 International Computers Limited Testing programmable logic arrays
US4780627A (en) * 1986-11-06 1988-10-25 International Computers Limited Testing programmable logic arrays
EP0388001A2 (en) * 1989-02-10 1990-09-19 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Testing method and apparatus for an integrated circuit
EP0388001A3 (en) * 1989-02-10 1991-08-14 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Testing method and apparatus for an integrated circuit
WO1993002415A1 (en) * 1991-07-25 1993-02-04 Siemens Aktiengesellschaft Device for testing electronic components of a unit interconnected according to the application
WO1993006497A1 (en) * 1991-09-23 1993-04-01 Digital Equipment Corporation Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip
GB2388199A (en) * 2002-04-30 2003-11-05 Samsung Electronics Co Ltd Multiple scan chains with pin sharing
GB2388199B (en) * 2002-04-30 2004-09-01 Samsung Electronics Co Ltd Multiple scan chains with pin sharing
GB2399890A (en) * 2002-04-30 2004-09-29 Samsung Electronics Co Ltd Multiple scan chains with output pin sharing
GB2399890B (en) * 2002-04-30 2005-06-15 Samsung Electronics Co Ltd Multiple scan chains with pin sharing
DE10241385A1 (en) * 2002-09-06 2004-03-25 Infineon Technologies Ag Integrated circuit for mobile radio equipment having function blocks with individual control systems
US7213183B2 (en) 2002-09-06 2007-05-01 Infineon Technologies Ag Integrated circuit

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Publication number Publication date Type
GB2121997B (en) 1985-10-09 grant
GB8315751D0 (en) 1983-07-13 grant

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PE20 Patent expired after termination of 20 years