JPS60159973A - Picture processing device - Google Patents

Abstract

PURPOSE:To obtain a device that can perform plural processes in parallel and at high speed by connecting alural processor elements that can act simultaneously and independently and memory elements by plural independent buses. CONSTITUTION:A processor 1 connects a picture memory 3, a picture processor 4 and a picture inputting device 5 through a control bus 2. The processor 1 gives operation indication to memory elements GM1-GMn of the picture memory 3 and processor elements PE1-PEm of the picture processor 4 through the control bus 2 according to process algorithm programmed in the processor 1. After completion of setting up of each memory element and each processor element, an element which received indication of input from picture data buses GB1-GBi outputs a start signal to relevant picture data bus. On receiving the start signal, the designated element outputs data of designated number of picture elements continuosly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an industrial image processing apparatus for processing video signals of an IT camera or the like.

[Technical background of the invention and its problems]

In recent years, image processing apparatuses have been increasingly used for industrial purposes, such as inspecting products for scratches. When applying an image processing device to industrial use, a high-speed device is required. Therefore, in conventional image processing apparatuses, a single processing function is sped up using locally parallel processors, and many such image processing apparatuses have been published. However, in the industrial application field, 3fX functions as an image processing device that can perform multiple processing functions in real time (IT
It is necessary to process images at a speed of 91 times (as compared to V-cameras), and currently there are no conventional image processing devices that can meet such demands.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above drawbacks, an object of the present invention is to provide an image processing apparatus that can perform multiple processes in parallel at high speed.

[Summary of the invention]

The present invention provides a plurality of processor elements for image processing that can operate simultaneously and independently, a plurality of memory elements for storing image data that can operate simultaneously and independently, and a plurality of processor elements that are coupled to these processor elements in a memory array. mutually independent image data buses, and each processor element and memory element is assigned its role;
and an image processing apparatus comprising: a processing processor which is coupled in a 4fA manner to provide a processing element i; and a control bus which couples the processing processor, the processor element and the memory element;
This is something that achieves the above purpose.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention. A processing processor (svp) 1 connects an image memory 3, an image processing processor 4, and an image input device 5 via a control bus 2. The image memory 3 includes a plurality of independently operable memory elements GM, ~
The image processing processor 4 is also composed of independently operable processor elements PE and PI. These memory elements GM, ~GM
The processor elements PE1-PE and the image input device 5 are connected to a plurality of independent image data buses GB, ~GBLK.
Connected.

The processing processor 1 manages the entire device, and the control bus 2 connects the processing processor 1, memory elements GM, ~GMJ, and processor elements) l, ~PE-.
This is to transfer control parameters such as start/stop to. Image data bus GB.

~GBL transfers image data, and an ITV camera or the like is generally connected to the image input device 5.

Next, the operation of this embodiment will be explained. According to the processing algorithm programmed in the processing processor 1, the processing processor 1 inputs each memory element (GM1 to GM) and I[i
Each processor element PE of 8i image processing processor 4
, ~PEmVc provides a motion finger system.

In this operation instruction, each memory element and each processor element connect to the image data bus GB, ~GB.

A memory element and a processor element t" that perform input/output to and from the image data bus QB, ~GBL are given an image data bus number (GBb) indicating which image data bus should be used. After the setup of each memory element GM, NGMn and each processor element PE, ~PEl!l by the processor IIC is completed, the input from the image data bus QB, ~G town is processed by the processor 1 and the element (tt)
In this case, a specific memory element or processor element) outputs a start signal to the corresponding image data bus. When the element (representing a specific memory element or processor element) that is instructed by the processor 1 to output data onto the same image data bus receives the start signal, it outputs data onto the image data bus. Continuously outputs the data of the number of pixels that have been set pixel by pixel. The input element that is instructed to input data from the image data bus is normally a processor element (or a memory element that is instructed to write), but it inputs data that is continuously passed to the image data bus in units of one pixel. At the same time, arithmetic processing is performed on a pixel by pixel basis, and the results are sequentially output to other image data buses.

The input element on the image data bus that transmits the result of this arithmetic processing receives this data, performs the next arithmetic processing, and further outputs the result of the processing onto another image data bus. By repeating the above operation for each input element, each element can process pixel by pixel in parallel, and a plurality of processing results can be obtained simultaneously.

Next, the above operation will be explained with reference to FIG. 2 (a more specific example will be explained with reference to FIG. 1 shows the process of processing by the image processing apparatus shown in FIG. 1, and also explains the process of storing the intermediate results in the image memory 3.

First, data from the image memories GM1 and GI111f2 are simultaneously read out by the processor 1, and these data are sent to the image data bus GB in units of pixels. The processor element PE□ has a processing unit 1
The data outputted onto the image data buses GB, GB, are assigned to inter-pixel operations, and the inter-pixel operations are performed based on this data, and the results are transferred to the image data buses GB.

Output to. The data output to the image data bus GB is input to the processor element PE and the memory element GM3. The processor element PH2 performs data conversion (binarization) 'fr,
The result of data conversion by this processor element PR2 is transferred to the image data bus G.
B, is output. The memory (GM) is allocated by the processor 1 to store the results of inter-pixel calculations, and stores data from the image data bus GBa.

Processor element PK, to 8-image data bus GB4
The data output to the next processor element PE
, and the memory element () M4 can be filled with human power.

This processor element L)I3. The processor element PB is configured to execute the histogram by the processor element 1, and the histogram is executed based on the input data.

Memory element GM, which is assigned by the processing processor to store data conversion results, stores data from image data bus GB4. Although not shown, it is also possible to input data to be processed next from a camera connected to the image input device 5 at the same timing as the above operation, independently of the above operation. be.

According to this embodiment, roles are assigned by the processor 1, and a plurality of roles can be operated simultaneously and independently!
By coupling the processing processor elements PE, ~PE and the image memory elements GM1 ~ GM, @S via a plurality of independent image data buses GB, ~GBLi,
A series of complex processes such as pixel-to-pixel calculations, data conversion, histograms, and storage of each processing result can be processed simultaneously. Furthermore, by driving each processor element and image memory element separately, a plurality of independent processes can be performed simultaneously.

Although the above embodiment has been described using an image processing device as an example, the 4 (1) structure, which organically connects multiple processors and multiple memories via multiple data buses, can also be applied to high-speed computers, etc. I can do it.

〔Effect of the invention〕

As described above, according to the image processing apparatus of the present invention, a plurality of simultaneously and independently operable processor elements and memory elements (t-m) are connected by independent buses, which can be assigned roles arbitrarily by the processing processor. By adopting this configuration, it is possible to realize the effect that multiple processes can be processed at high speed and in parallel.

[Brief explanation of the drawing]

Figure 1 shows ll! of the present invention! FIG. 2 is a block diagram showing an example of the capabilities of the Ii image processing apparatus. FIG. 2 is an operational process diagram when a series of complex processes are performed by the image processing apparatus shown in FIG. 1... Processor 2... Control bus 5... Image input device GB, ~GB,... Image data bus GM, ~GM,... Memory element PR1-PE,
...Processor Element Agent Patent Attorney Book 1)
Takashi

Claims (1)

[Claims] A processor element for image processing of counts that can operate simultaneously and independently, a memory element for storing image data of a number of images that can operate simultaneously and independently, and a plurality of independent images that combine these processor elements and memory elements. a data bus, a processing processor that gives roles to each of the processor elements and memory elements, and organically connects these elements to provide a processing procedure; and a control that connects the processor, the processor elements, and the memory element. An image processing device characterized by comprising a bus and a bus.