JPS6343484A - Picture processor - Google Patents

Abstract

PURPOSE:To easily and rapidly constitute a processing circuit suitable for the picture processing in the respective uses by switching and controlling the selection of a connection between a picture signal line and the respective circuit blocks with a software. CONSTITUTION:A picture signal bus BS includes plural picture signal lines l1-ln, which are constituted so that the picture signals can be respectively and separately transmitted. In the input-output part of the respective blocks, select switch circuits SW11, SW12... are provided to connect the inputs of the respective blocks to optional picture signal lines l1-ln. Switching and controlling of the select switch circuits is programmed with the software, and after determining the constitution of the processing circuit the realization of the circuit can be extremely rapidly and easily executed by the program.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to an image processing system for obtaining data regarding the shape, position, orientation, etc. of an object from an image signal of the object obtained by a television camera or the like. It is used for sorting, positioning, and inspecting objects.

(Background technology) Conventionally, when an object is photographed with a television camera and the obtained image signal is image-processed to obtain information such as the shape and position of the object, the first step is to In order to obtain the optimal image signal, we examine and design the image processing circuit block, then design and manufacture the actual circuit, and then,
Software was added and used for actual applications.

(Purpose of the Invention) In the development steps of conventional image processing devices as described above, the configurations of the required processing circuits are often very similar, and the design and manufacturing of the circuits (also in 'V) are extremely difficult. Most of the items can be used over and over again.

The present invention has been made based on such knowledge, and its purpose is to prepare a plurality of circuit blocks in which processing circuits are modularized according to purpose or function, and to recycle these as appropriate depending on the purpose. The object of the present invention is to provide an image processing device in which a processing circuit can be quickly constructed by selecting and combining (13) necessary processing circuits, and one piece of hardware can be switched and used for multiple purposes.

(Disclosure of the Invention) Hereinafter, the configuration of the present invention will be explained with reference to illustrated embodiments.
λ* (=f As shown on page I21, TV camera C
An image processing device that converts image signals input from Ml and CM2 into binary signals at an arbitrary threshold level and extracts a characteristic rR11 of an object from an image of the obtained binary signals, Binarization processing units CPI, CF2 . ...and frame memories F M 1 and F M 2 for temporarily storing image signals.
, . . . and 7-trix calculation units MXI, MX2 . . . , a plurality of image signal lines 1.
A select switch circuit for selectively connecting the image signal lines 11 to 1n and each circuit block in the image signal bus BS by disposing an image signal bus [3S between the circuit blocks and connecting the image signal lines 11 to 1n in the image signal bus BS to each circuit block. SW 11. SW
l 2 , SW 21 , SW 22 ,...
・Equipped with a memory select switch circuit sw, , , sw,
□, SW21.

SW22, .

The circuit blocks shown in FIGS. 1(a) to (i>) indicate circuit elements for constructing an image processing circuit.

The figure (a) shows a television camera CM i for photographing an object to be ffi and extracts an image signal, and the figure (b) shows a binarization processing unit CPi for converting the image signal into two values. c) is a matrix calculation unit MXi for performing arithmetic processing such as noise removal processing, B'J expansion processing, and reduction processing on the binary f-valued signal; Frame memory FMi for storing information, same figure (e)
(f) is a window generation unit WGi for generating a window area that limits the processing range, and (f) is a logic gate unit L for performing logical operations between binarized image signals.
Gi, (g) is a counter part CTi for counting the area of the "white" part in the binarized image signal;
(11) in the figure shows a line element extraction unit LNi that extracts line element data for calculating data such as position and shape;
) is a monitor display section MNi for performing monitor display. Here, i is an integer of 1 or more, for example, the binarization processing units CPi, CF2 . . . , each circuit block is used in plural numbers.

FIG. 2 shows a circuit configuration for switching each block. A three-image signal bus BS includes a plurality of image signal lines 11
Contains ~Iin. Each of the image signal lines 1° to In is configured to be able to transmit image signals independently. The input/output section of each block includes select switch circuits S W + +, S W +2, S
W 21 , S W 2□, . . . are provided, and the input and output of each block is connected to an arbitrary image signal line 1. -In can be connected.

The select switch circuit S W Il, S W I
2, SW211, SW221, etc. can be programmed by software, and after determining the configuration of the processing circuit, the circuit can be implemented extremely quickly and easily. Note that the select switch circuit S W +1. S W l 2 , S
As a device for programming the switching of W 21 , S W 2□, ... by software,
For example, storage data stored in a plurality of storage units provided in a microcomputer and each select switch circuit sw
, , sw, □, SW, , SW2□, ... are associated with each other, data is set in each storage section from the microcomputer keyboard, and switching control is performed according to the contents of the storage section. Select switch circuit sw, , sw, □, s to select the signal from the output port of the microcomputer
w2. ．． sw.

2, . . . can be used.

In addition, the processing circuit is designed using CAD, and the circuit diagram of the processing circuit is output from the CAD. At the same time, seven switch circuits SW + +, SW1□, SW2 . ．．
5W22, . . . may be configured to output switching signals.

Hereinafter, a configuration method for an image processing circuit will be explained using a specific example.

The configuration shown in Figure 3 (,) is an example of the simplest configuration of an image processing circuit, in which the image signal captured in one TV camera commercial is converted into binary 1hi-13 by the binarization processing unit CPI.
Noise removal processing is performed through the AL and matrix calculation section MX1, and the image is taken into the frame memory FM1.The subsequent processing is performed on the image taken into the frame memory FMI.

The image stored in the frame memory FMI is displayed on the monitor at the reception part MNI.

The configuration shown in Figure 3 (1+) is for one TV camera commercial.
The image signal taken in from I is converted into a binarized signal by binarization processing units CPI and CF2 each having a different binarization level, noise removal processing is performed by matrix calculation units MXi and MX2, and window generation unit WG 1.WG
2, for the masked parts of the windows set in different locations, the counter part CTI, CT2
This makes it a processing circuit that counts the number of points.

The configuration shown in No. 3 [J(c) is for one TV camera commercial
The double-headed signal converged from I is converted into a binary signal by the binary 1hi processing unit CP1, and subjected to noise removal processing by the matrix calculation unit MXI. It is a processing circuit that extracts line element data for calculating data such as position 1, shape, etc. in an element extraction unit LNI, and displays the area on a monitor display unit MNI.

The configuration shown in FIG. 3(d) is such that the image signal received from the television camera CM1 is binarized by the binarization processing unit CPI, and the image signal taken in from the television camera CM2 of another system is binarized. The fE signal is binarized in the 1hi processing unit CP2, the binarized signal of either system is reduced in the matrix calculation unit MXI, and the fE is generated in the window generation unit WG2.
It is a processing circuit that performs an AND operation between the I-area signal and the output signal of the lix calculation unit MXI from 71 in the logic gate unit LGI, stores the result in the frame memory FMI, and displays it on the monitor display unit MNI. ing.

The processing circuits shown in FIGS. 3(,) to (d) above are merely examples, and the select switch circuits S W l+ , S W
l 2 , SW 2. , SW, □, . . . , it goes without saying that any other processing circuit can be configured.

In addition to the television camera shown in the embodiment, an image input device such as Image League may be used as the image input device.

(Effects of the Invention) As described above, the present invention includes a plurality of circuit block groups for image processing, and a select switch for selecting the connection between the image signal line and each circuit block in the image signal bus. Since the circuits are switched and controlled by software, it is possible to easily and quickly configure processing circuits suitable for various types of image processing by appropriately selecting and combining circuit blocks according to the application. This is effective, and it also has the effect that the same hardware can be switched and used for multiple purposes.

[Brief explanation of the drawing]

FIGS. 1(a) to (i) are block diagrams showing processing circuits used in an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a main circuit diagram of the same embodiment, and FIG. ) to (d) are block diagrams showing a configuration example of an image processing apparatus using the above embodiment. CMI, CM2 are television cameras, CPI, CF2 are binarization processing units, MXI, MX2 are matrix calculation units, FM
I, FM2 is frame memory, SW++, SW, □,
S W 21 and S W z□ are select switch circuits, and PG is a programming device.

Claims (1)

[Claims] (1) An image processing device that converts an image signal input from an image input device into a binarized signal at an arbitrary threshold level, and extracts feature quantities of an object from an image of the obtained binarized signal, , comprising a circuit block group including a comparison circuit for converting an image signal into a binary signal, a storage circuit for temporarily storing the image signal, and an arithmetic circuit for performing operations on the binary signal. , an image signal bus composed of a plurality of image signal lines is disposed between the circuit block groups, and a select switch circuit is provided for selectively connecting the image signal line and each circuit block in the image signal bus. An image processing apparatus comprising: a device for programming switching control of the select switch circuit using software.