JP2501799B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus for obtaining data relating to the shape, position, orientation, etc. of an object from an image signal of the object obtained by a television camera or the like. Yes, it is used to select, position, and inspect objects.

(Background Art) Conventionally, an object is photographed by a TV camera,
When processing the obtained image signal to obtain the shape and position information of the target object, first consider the image processing circuit block according to the application so that the optimum image signal can be obtained. It was necessary to design, and it took time to examine and design the circuit block. In order to solve this, "image processing for each application" is calculated using complicated software.
An apparatus that realizes processing is also known, but such an apparatus has a problem of low processing speed.

Further, in Japanese Patent Laid-Open No. 60-159973, in order to realize an image processing device capable of processing a plurality of processes at high speed and in parallel, a plurality of processor elements and a plurality of memory elements are provided by a plurality of data buses. It has been proposed to adopt a combined configuration, but since this is processed by a processing algorithm that is programmed to achieve high speed and parallelism, it is limited in usage and adaptable to various things. There was a problem that I could not do it.

(Object of the Invention) In the development steps of the conventional image processing apparatus as described above, the configurations of the processing circuits required are very similar in many cases, and most of the applications in the circuit design / manufacturing are also used. , Can be used almost repeatedly.

The present invention has been made on the basis of such knowledge, and an object thereof is to prepare a plurality of circuit blocks in which processing circuits are modularized according to use or function, and select these appropriately according to use. It is an object of the present invention to provide an image processing apparatus in which a necessary processing circuit can be quickly constructed by combining the above-described elements and one piece of hardware can be switched and used for multiple purposes.

(Disclosure of the Invention) Hereinafter, the configuration of the present invention will be described with reference to the illustrated embodiments. As shown in the accompanying drawings, FIGS. 2 and 3 (a) to (d), the input is made from the television cameras CM1 and CM2. The image signal is converted into a binary signal at an arbitrary threshold level, and the obtained 2
An image processing apparatus for extracting a feature amount such as a dimension, an area, and a center of gravity of an object from an image of a binarized signal, which is a binarized processing block CP1, CP2, ... For converting the image signal into a binarized signal.
And frame memory blocks FM1, FM2, ... For temporarily storing image signals, and n × m for binarized signals
Matrix operation block that performs logical operation on neighboring pixels
An image signal bus BS including a plurality of image signal lines l _{1 to} l _n is provided between the circuit blocks, and the image signal lines in the image signal bus BS are provided with circuit blocks such as MX1, MX2, ....
Select switch circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , ... For selectively connecting l _{1 to} l _n to each circuit block are provided, and the select switch circuits SW ₁₁ , SW ₁₂ , SW _{21 are provided.} ， S
It is equipped with a programming device PG for programming the switching control of W ₂₂ , ... With the assistance of a computer. This programming device PG CA
It is performed by D, and the circuit diagram of the processing circuit is output from CAD, and at the same time, the select switch circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ ,
Input means for at least an operator to select a circuit block and to specify a connection relationship between the selected circuit blocks in order to output the switching signal of ..., The circuit block selected by the input means and the connection relationship Is abbreviated as shown in FIGS. 3 (a) to 3 (d), and the select switch is configured to realize a specified connection between the circuit block selected by the input means and the means for displaying. It is equipped with means for controlling the switching of the circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , ....

The circuit blocks shown in FIGS. 1A to 1I show some examples of the circuit blocks for forming the image processing circuit. The figure (a) is a television camera CMi for photographing an object and taking out an image signal, and the figure (b) is an image signal 2
A binarization processing block CPi for binarization, FIG. 6C shows noise removal processing and dilation processing for the binarized signal,
A matrix calculation block MXi for performing calculation processing such as reduction processing, FIG. 6D shows a frame memory block FMi for temporarily storing image signals, and FIG.
Is a window generation block WGI for generating a window region that limits the processing range, FIG. 6F is a logic gate block LGi for executing a logical operation between binarized image signals, and FIG. Is a counter block CTi for counting the area of the "white" part in the binarized image signal, and FIG. 6 (h) corresponds to the part occupied by the target object for each scanning line for calculating data such as position and shape. A line element extraction block LNi for extracting line element data, and a monitor display block MNi for performing monitor display are shown in FIG. Here, i is an integer of 1 or more, and a plurality of circuit blocks are prepared, for example, binarization processing blocks CP1, CP2, ....

FIG. 2 shows a circuit configuration for switching the blocks. The image signal bus BS includes a plurality of image signal lines l ₁ ...
contains l _n . Each of the image signal lines l _{1 to} l _n is configured to be able to independently transmit an image signal. Select switch circuit SW is connected to the input / output section of each block.
₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , ... Are provided so that the input / output of each block can be connected to arbitrary image signal lines l _{1 to} l _n .

The select switch circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ ,
The switching control of ... is performed by a design device (CAD) supported by a computer. That is, the design of the processing circuit is performed by the CAD, and the circuit diagram of the processing circuit (for example, see FIGS. 3A to 3D) is output from the CAD, and at the same time, the select switch circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , SW By outputting the switching signal of ₂₂ , ..., After determining the configuration of the processing circuit on the CAD screen, the circuit can be realized quickly and easily. Incidentally, the design and the selection switch circuit SW ₁₁ of the processing circuit by _{CAD, SW 12, SW 21,} SW 22, the means for interlocking the ... switching, for example, any circuit block and its connection relationship with an input means of the computer The selected data is displayed in abbreviated form / schematically as a block diagram as shown in FIGS. 3 (a) to 3 (d), and the stored data stored in a plurality of storage units provided in the computer for the display is displayed. Use
The state of each select switch circuit SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , ... is determined, and the switching signal is output from the output port of the computer to the select switch circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ ,. Good.

Hereinafter, a method of configuring the image processing circuit will be described with a specific example.

The configuration shown in FIG. 3 (a) is an example of the configuration of the simplest image processing circuit. The image signal captured from the television camera CM1 is converted into a binary signal by the binarization processing block CP1 and matrix calculation is performed. Noise removal processing is performed through the block MX1 and captured in the frame memory block FM1. Subsequent processing is this frame memory block FM
Perform on the image captured in 1. The image stored in the frame memory block FM1 is displayed on the monitor display block MN1.

The configuration shown in FIG. 3 (b) has one TV camera CM1.
The image signal taken in from is converted into a binarized signal by the binarization processing blocks CP1 and CP2 each having a different binarization level, noise removal processing is performed by the matrix operation blocks MX1 and MX2, and the window generation block WG1, By the counter block CT1, CT2, about the part masked by the window set in each different place by WG2,
It is a processing circuit that counts the area value.

The configuration shown in FIG. 3 (c) is one TV camera CM1.
The image signal taken in from is converted into a binary signal by the binary processing block CP1, and the matrix operation block MX1
Noise removal processing is performed in the window generation block WG
Line element extraction block LN1 for the area set in 1
In this processing circuit, line element data for calculating data such as position and shape is extracted and the display of the area is performed by the monitor display block MN1.

The configuration shown in FIG. 3 (d) binarizes the image signal taken in from the TV camera CM1 in the binarization processing block CP1 and another binarized image signal taken in from the TV camera CM2 of another system. Binarization is performed by the conversion processing block CP2,
The binary signal of either system is reduced by the matrix calculation block MX1, and the area signal generated by the window generation block WG2 and the matrix calculation block MX1.
The processing circuit performs AND operation with the output signal of the logic gate block LG1, stores the result in the frame memory block FM1, and displays it in the monitor display block MN1.

The above processing circuits shown in FIGS. 3A to 3D are merely examples, and the select switch circuits SW ₁₁ , SW ₁₂ , SW ₂₁ , and S.
It goes without saying that another arbitrary processing circuit can be configured by switching control of W ₂₂ ,. Further, the processing result data is read by a microcomputer, and arithmetic processing, determination, output and the like are performed.

In addition to the television camera shown in the embodiment, an image reader such as an image reader may be used as the image input device.

(Advantages of the Invention) As described above, in the present invention, a select switch for selecting a connection between an image signal line and each circuit block in an image signal bus, which includes a plurality of circuit block groups for image processing. Since a circuit is provided and the design of the processing circuit is performed by CAD, and the circuit diagram of the processing circuit is output from the CAD, at the same time, the switching signal of the select switch circuit is output so as to realize the circuit. By appropriately selecting and combining circuit blocks according to the application, there is an effect that a processing circuit suitable for image processing for each application can be configured easily and quickly, and the same hardware can be used for multiple purposes. There is an effect that they can be switched and used. Further, since image processing for each application is executed by hardware, there is an effect that it can be executed at a processing speed almost equal to that in the case where dedicated circuits are individually designed and manufactured.

[Brief description of drawings]

1 (a) to (i) are block diagrams showing a processing circuit used in an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a main part of the same embodiment, and FIG. 3 (a). 8A to 8D are block diagrams showing a configuration example of an image processing apparatus using the above-described embodiment. CM1 and CM2 are TV cameras, CP1 and CP2 are binarization processing blocks, MX1 and MX2 are matrix calculation blocks, FM1 and FM2 are frame memory blocks, SW ₁₁ , SW ₁₂ , SW ₂₁ and SW ₂₂ are select switch circuits, and PG Is a programming device.

Claims (1)

(57) [Claims] 1. An image processing device for converting an image signal input from an image input device into a binarized signal at an arbitrary threshold level and extracting a feature amount of an object from an image of the obtained binarized signal. Therefore, a binarization processing block including a comparison circuit for converting an image signal into a binarized signal, a frame memory block including a storage circuit for temporarily storing an image signal, and an operation for a binarized signal A circuit block such as a matrix calculation block including an arithmetic circuit for performing
An image signal bus composed of a plurality of image signal lines is arranged between the circuit blocks, and a select switch circuit for selectively connecting the image signal lines in the image signal bus to the circuit blocks is provided. Input means for the operator to select a circuit block and to specify the connection relationship between the selected circuit blocks, and means for displaying the circuit block selected by the input means and the connection relationship in abbreviated form / schematic representation, An image processing apparatus comprising: a CAD device comprising means for controlling switching of the select switch circuit so that a specified connection relationship is realized between circuit blocks selected by input means.