JP2857421B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for use in image processing such as a copying machine and a facsimile.

[Conventional technology]

One of the processes of image information is, for example, a hollowing-out process (contour extraction process) for deleting characters and the like included in the image information.
There is. Conventionally, various methods have been known for this processing. For example, XOR processing between an original image and its blurred image, or original image and MTF (Modulation
Transfer Function: Modulation transfer function).

[Problems to be solved by the invention]

However, in the above-described conventional image processing apparatus, the width and shape of the hollow area cannot be freely set, and the processing is limited. For this reason, the effect of the hollowing process could not be sufficiently exhibited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances of the related art, and has as its object to provide an image processing apparatus capable of arbitrarily setting a blanking width.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, in an image processing apparatus that performs a blanking process of input image data, a matrix type setting unit that sets an arbitrary matrix shape and an optional blanking width are set. Matrix size selection means, by referring to the matrix according to the settings of the matrix type setting means and the matrix size selection means, the input image data with an arbitrary matrix shape and an arbitrary hollow width And a processing unit for performing a blanking process.

[Action]

According to the above-mentioned means, by setting the shape of the matrix by the matrix type setting means and setting the blanking width by the matrix size selecting means, the blanking processing can be performed with an arbitrary matrix shape and blanking width.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

Data binarization unit 1 is provided for binarizing the digital image signal D _i, the reference matrix extractor 2 is connected to the data binarization unit 1. The reference matrix extracting unit 2 is connected to a hollow portion 3 for performing a hollow process. Further, the reference matrix extracting unit 2 includes a matrix type setting unit 4 for setting a matrix type such as a square or a circle, and also a matrix size for selecting a matrix size such as one stage (one pixel) or two stages (two pixels). The matrix size selection unit 5 is connected.

FIG. 2 is a circuit diagram showing a detailed configuration of the matrix size selection unit 5.

The matrix size selection unit 5 is mainly composed of an AND circuit 51, a power supply voltage (for example, +5 V) is applied to one input terminal via a resistor 52, and a size selection signal S _S is applied to the other input terminal. Is entered. The output voltage of the resistor 52 becomes the first-stage selection signal 5a, and the output signal of the AND circuit 51 becomes the second-stage selection signal 5b. In addition, signal S _S is the size select signal 5c as it is.

FIG. 3 shows a setting table of the matrix type setting section 4. Select one set in advance according to the type and size of the matrix (type selection signal S _T , signals 5a, 5b, 5c
), The pixel in the matrix to be referred to is set to “1”. In this case, the selection can be made for the elements P1 to P25. For example, the square shown in FIG. 4 or the circle shown in FIG. 5 using the signal 5a, the square shown in FIG. The circle shown in FIG. 7 is selected.

FIG. 8 is a block diagram showing the details of the reference matrix extraction unit 2, which is composed of 25 (L1 to L25) latches 21 and buffer memories 22, 23, 24, 25 for one line.
The latches 21 are grouped in groups of five, and the second and subsequent latches are connected to one buffer memory. Latch L1 ~ L2
5 is conditioned, for example, latch L1
In this case, the circuit shown in FIG. 9 is connected. Latch L1
9 is connected to one input terminal of the AND circuit 26 in FIG. 9 and the other input terminal is connected to the element shown in FIG.
P1 is applied to output an output signal _SL1 .

FIG. 10 is a block diagram showing details of the hollow portion 3;
A 25-input NAND circuit 31 to which output signals S _{L1 to} S _L25 based on the outputs of the latches _{L1 to L25} are input, and an AND circuit that obtains output data by taking the logical product of the output signal of the NAND circuit 31 and the output original data It consists of 32.

Next, the operation of the embodiment having the above configuration will be described. Here, a case will be described in which a square and a circular matrix type are selected and set, and the matrix size is selectively set and set to one step (one pixel) and two steps (two pixels) to perform hollowing.

First, the input digital image information is binarized by the data binarization unit 1. The data binarization unit 1 sets the output binary data to "1" when the most significant bit of the input data is "1". In the matrix size selection unit 5, a 1-bit size selection signal _SS is input by operating a dip switch or the like. This size selection signal S
_{When S} is "0", a one-stage size is designated, and when "1", a two-stage size is designated. As shown in FIG.
a, 5b, and 5c are output. The signals 5a and 5b are input to the matrix type setting unit 4, and the signal 5c is input to the matrix type setting unit 4 and the reference matrix extraction unit 2.

The matrix type setting section 4 is shown in FIGS.
FIG selection is set based on any one of FIG. 7 to output and type selection signal S _T of the matrix size select section 5. Based on this selection, the reference matrix extraction unit 2
The output signal of the value conversion unit 1 is developed as shown in FIG. For example, in the system of the latch L1, a "1" level signal is output only when the output signal is "1" and P1 is "1". However, when the matrix size is set to the first stage (one pixel) (that is, the output signal 5c of the matrix size selection unit 5).
Is "0"), latches L4, L5, L9, L10, L14, L15, L16-
Unconditionally set each output of L25 to "1".

In addition, as the output original, L7 is selected when the hollow width is the first stage, and L13 is selected when the hollow width is the second stage. In this case, the circuits connected to L7 and L13 are different from FIG. 9 and are as shown in FIG.

Each of 27, 28, 29, and 30 is a two-input AND circuit. The signal 5c and the output signal of the latch L7 are input to the AND circuit 27,
The output signals of the signals 5c and L13 are input to the AND circuit. The output signal of the latch L7 and the signal of the element P7 are input to the AND circuit 29, and the output signal of the L13 and the signal of the element P13 are input to the AND circuit 30. AND circuit 27 and
An OR circuit 31 is connected to the output terminal 28, and outputs "1" level if one of the inputs is "1".

In this circuit, the output of the OR circuit 31 becomes "1" when the outputs of the signals 5c and L13 are both "1" or when the signal 5c is "0" and the output of L13 is "1".

Next, based on the output signal of the reference matrix extraction unit 2, the centering unit 3 performs centering processing.

When all of the input signals S _{L1 to} S _L25 are “1”, the NAND
The circuit 31 outputs a “0” level signal, the output of the AND circuit 32 goes to the “0” level, and a signal subjected to the blanking processing is output.

In the present invention, a hollowing-out process having characteristics as shown in FIGS. 12 and 13 is also possible. For example, when a square reference matrix is used for a cross-shaped original image as shown in FIG. 12 (a), a hollow image as shown in FIG. 12 (b) or FIG. When a circular reference matrix is used for a circular original image as in (a), a hollow image as shown in (b) or (c) is obtained (in the figure, hatched lines are binary data). Indicates the "1" part). The difference between the diagrams (b) and (c) arises depending on whether the matrix is angular or round.

FIG. 14 shows the trimming process of a triangular original image. By changing the size of the triangular reference matrix with respect to the original image of FIG. 14 (a), a hollowing process as shown in FIGS. 14 (b) and 14 (c) having different thicknesses can be obtained.

〔The invention's effect〕

As described above, according to the present invention, the blanking process can be performed with an arbitrary matrix shape and a blanking width.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention, FIG. 2 is a circuit diagram showing a detailed configuration of a matrix size selecting section, and FIG. 3 is an explanatory view showing a setting table of a matrix type setting section. , FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are explanatory diagrams of a matrix size selected and set by a matrix type setting unit, FIG. 8 is a block diagram showing details of a reference matrix extraction unit, and FIG. Is a circuit diagram showing an example of the conditioning circuit, FIG. 10 is a block diagram showing details of the hollow portion, FIG. 11 is a circuit diagram showing another example of the conditioning circuit, and FIGS. 12 (a), (b), and FIG. 13 (c) is an explanatory diagram showing a blanking process for a cross-shaped original image.
14 (b) and (c) are explanatory diagrams showing a hollowing process for a circular original image, and FIGS. 14 (a), (b) and (c) are explanatory diagrams showing a hollowing process for a triangular original image. . 1. Data binarization unit 2. Reference matrix extraction unit
3 ... hollow section, 4 ... matrix type setting section, 5 ...
... Matrix size selection section.

Claims (1)

(57) [Claims] 1. An image processing apparatus for performing a blanking process on input image data, comprising: a matrix type setting unit for setting an arbitrary matrix shape; a matrix size selecting unit for setting a blanking width; Processing means for performing a blanking process on the input image data with an arbitrary matrix shape and an arbitrary blanking width by referring to the matrix according to the settings of the matrix type setting means and the matrix size selecting means An image processing apparatus, comprising: