JPS61131072A - Picture processor - Google Patents

Abstract

PURPOSE:To attain highly efficient processing small-sized picture bus constitution by forming plural multilevel pictures consisting of plural bits and plural binary picture buses each of which consists of one bit and to use these buses properly in accordance with the data length of data. CONSTITUTION:The I/O terminals of picture processor modules 34-38 for executing picture processing based upon a pipeline system are connected to multilevel buses 41-44 each of which consists of 8 bits and binary picture buses 51-54 each of which consists of 1 bit. The data conversion module 34 and the space filter module 35 process 8-bit data, but the data conversion module 36 can process data through the binary picture bus because its output is 1-bit data. The picture memory 38 converts the binary data of 1 bit into the binary data (00H, FFH) of 8 bits and writes the 8-bit binary data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing apparatus in which image processing is performed by pipeline processing using a plurality of image processing processor modules.

[Technical Background of the Invention and Problems Therewith] Generally, this type of image processing apparatus is configured as shown in FIG. In FIG. 2, a system processor 11 forming the center of the apparatus includes an image input module 13 that inputs images from an ITV camera 12, a data conversion module 14 that performs shading correction, etc., a spatial filter module 15, and a data conversion module that performs binarization. module 1
6, logical filter module 17, and image memory 1
8 is controlled via a system bus, 20. Image data input from the image input module 13 is processed in a pipeline manner by image processing processor modules such as a data conversion module 14, a spatial filter module 15, a data conversion module 16, a logical filter module 17, and an image memory 18. It is processed.

That is, for example, 8-bit multivalued data input by the image input module 13 is supplied to the data conversion module 14 via the 8-bit image bus 21. The data conversion module 14 performs shading correction and the like on the data from the image input module 13. The data conversion result (8 bits) of the data conversion module 14 is supplied to the spatial filter module 15 via the image bus 22. Spatial filter module 15 performs spatial filtering using the data from data conversion module 14 . The filtering result (8 bits) of the spatial filter module 15 is supplied to the data conversion module 16 via the image bus 23. The data conversion module 16 converts the data from the spatial filter module 15 into 21ii
8-bit all 0 or all 1 data 00
H/FFH (H indicates hexadecimal representation) is supplied to the logic filter module 17 via the image bus 24. The logical filter module 11 performs logical filtering on the data from the data conversion module 16. The filtering result (8 bits of 00H or FFH) of the logical filter module 17 is supplied to the image memory 18 via the image bus 25 and written into the memory 18.

As described above, the image processing apparatus shown in FIG. 2 has a problem in that five image buses 21 to 25 are required to perform image processing by pipeline processing.

Therefore, as shown in FIG.
It is also possible to set the number of buses to four (24), but in this case, it is necessary to temporarily stop the filtering process of the logical filter module 17, wait for the bus to be released, and then continue the subsequent process. There was a problem that made it impossible to perform efficient pipeline processing.

[Object of the invention] This invention was made in view of the above circumstances. , □Yo, Error 5-) LtfF, 8n□1o□A The object of the present invention is to provide an image processing device that can efficiently perform multi-stage pipeline processing using 10 setters even with a small-scale image bus configuration. 1 [Summary of the Invention] In the present invention, a plurality of multi-value image buses each consisting of a plurality of bits, a plurality of binary image buses each consisting of one bit, and a plurality of image processing processor modules each including an image memory are provided. Each image processing processor module executes pipeline processing using one of the plurality of multivalued image buses and the plurality of binary image buses according to the data length of the handled data. In particular, the image memory, which is one of the image processing processor modules, uses one of the plurality of binary image buses at the time of memory write, and all data is output according to 1.0 of the binary data on the binary image bus. Write 1 or all 0 data. Further, the image memory uses one of the plurality of multivalued image buses when reading the memory.

[Embodiment of the Invention] FIG. 1 shows the configuration of an image processing apparatus according to an embodiment of the invention, and 31 is a system processor that forms the center of the apparatus. 32 is an ITV camera, and 33 is an image input module that inputs images from the rTV camera 32. 3
4 to 38 are image processing processor modules that perform image processing using a pipeline method. Specifically, 34
35 is a data conversion module that performs shading correction, etc., and a spatial filter module 35 that performs spatial filtering. Further, 36 is a data conversion module that performs binarization, 31 is a logical filter module that performs logical filtering, and 38 is an image memory. The image input module 33, data conversion module 34, spatial filter module 35, data conversion module 36, logical filter module 31, and image memory 38 are as follows:
It is connected to the system processor 31 by a system bus 40.

41 to 44 are image buses for 8-bit multi-value data (hereinafter referred to as multi-value image buses), and 51 to 54 are image buses for 1-bit binary data (hereinafter referred to as binary image buses). . In this example, the multilevel image bus 41 includes the output of the image input module 33 and the data conversion module 34.
The input of the data conversion module 34 and the spatial filter module 35 are connected to the multivalued image bus 42.
input is connected.

The output of the spatial filter module 35 and the input of the data conversion module 36 are connected to the multivalued image bus 43.
The output of the image memory 38 is connected to the multivalued image bus 44 . The binary image bus 51 also includes a data conversion module 3.
The output of the logic filter module 37 and the input of the image memory 38 are connected to the binary image bus 52.

Next, the operation of the above configuration will be explained.

The system processor 11 includes an image input module 33
, data conversion module 34 , spatial filter module 35 , data conversion module 36 , logical filter module 31 , and image memory 38 are connected to the system bus 40 .
Control via. Therefore, the image input module 33
The input image data is sent to the data conversion module 3.
4, the spatial filter module 35, the data conversion module 36, the logical filter module 37, and the image memory 38 process in a pipeline manner.

That is, for example, 8-bit multi-value data inputted by the image input module 33 is supplied to the data conversion module 34 via the multi-value image bus 41. The data conversion module 34 performs shading correction and the like on the data from the image input module 33, and supplies the result (8 bits) to the spatial filter module 35 via the multi-valued image bus 42. The spatial filter module 35 spatially filters the data from the data conversion module 34 and supplies the result (8 bits) to the data conversion module 36 via the multilevel image bus 43. The operations up to this point are similar to those of the image processing apparatus shown in FIGS. M2 and 3.

The data conversion module 36 binarizes the data from the spatial filter module 35 to obtain 1-bit binary data. The data conversion module 36
Value data is supplied to the logic filter module 37 via the binary image bus 51. The logical filter module 31 is
Logical filtering is performed using the 1-bit binary data from the data conversion module 36, and the result (1-bit 2Wi data) is supplied to the image memory 38 via the binary image bus 52.

In this way, the binary data handled by the data conversion module 36 and the logical filter module 37 is 1 bit, unlike the data conversion module 16 and the logical filter module 17 in FIGS. 2 and 3. By providing a 1-bit configuration image bus such as the binary image bus 51.52, there is no need to use 8-bit binary data (OOH/FFH) in conjunction with the 8-bit image bus as in the past. It depends.

The image memory 38 converts the 1-bit binary data from the logical filter module 37 into 8-bit binary data and writes it into its storage area. That is, the image memory 38 is
If the 1-bit binary data from the logic filter module 37 is 0, 8-bit all-0 data (OOH)
is written, and if the 1-bit binary data from the logical filter module 31 is 1, 8-bit all-1 data (FFH) is written.

The above operation is similar to that of the image processing device shown in FIG.
Pipeline processing allows continuous repetition. That is, according to this embodiment, the data conversion module 3
4. By using the multi-value image bus and the 2i1 image bus depending on the data length of the data handled by the spatial filter module 35, data conversion module 36, logical filter module 37 and image memory 38, an 8-bit multi-value image can be created. Only three buses 41 to 43 and two 1-bit binary image buses 51 and 52 have a total of 26 bits.
Pipeline processing equivalent to using a 5-tree (40 bits) can be performed.

Read data from the image memory 38, that is, 8-bit all 0 data (OOH) or all 1 data (FFH)
) is sent to the multilevel image bus 44.

Note that the numbers of image processing processor modules, multivalued image buses, and binary image buses are not limited to those in the embodiments described above, and can be increased or decreased as necessary.

[Effects of the Invention] As detailed above, according to the present invention, multi-stage pipeline processing by a plurality of modularized image processing processors can be efficiently performed even with a small-scale image bus configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing a conventional example. 33... Image input module, 34. 36... Data conversion module, 35... Spatial filter module, 37... Logical filter module, 38... Image memory, 41-44... Multivalued image Bus, 51-54・
...Binary image bus. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] In an image processing device that performs image processing using a pipeline method, a plurality of multivalued image buses each consisting of a plurality of bits,
executing pipeline processing using one of a plurality of binary image buses each consisting of one bit, the plurality of multivalued image buses and the plurality of binary image buses according to the data length of the handled data; and a plurality of image processing processor modules including an image memory, wherein the image memory uses one of the plurality of binary image buses at the time of memory writing, and one of the binary data on the binary image bus. An image processing device characterized in that it is configured to write all 1 or all 0 data in accordance with 0, and to use one of the plurality of multivalued image buses when reading a memory.