JPS62266678A - Image processor - Google Patents

Abstract

PURPOSE:To make real time processing possible by supplying picture element data to plural processors necessary for processing the picture element data simultaneously. CONSTITUTION:Whole picture data are divided into blocks B of 20 horizontal line each and 20 processors are provided to give one processor charge of neighborhood processing of data of one line of each block B. Input data to processors for processing become image data read out once from an input image memory. However, input side data transfer rate is made equal to output side by devising the order of reading of picture elements from the input image memory, and transferring one picture element data to necessary processors simultaneously, and using registers provided in the inputting step of each processor.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an image processing device that has a plurality of arithmetic processors and is capable of performing various types of image processing using these plurality of processors, and particularly relates to an image processing device that has a plurality of arithmetic processors and can perform various types of image processing. This invention relates to a technique for performing so-called neighborhood processing using peripheral pixel data.

[Essentials of invention]

When performing so-called neighborhood processing using a plurality of processors, this invention supplies pixel data simultaneously to the plurality of processors that require the pixel data for processing, thereby improving input end data transfer rate and output side data transfer rate during neighborhood processing. This allows the data transfer rate to be almost the same.

[Conventional technology]

Various video image processing systems have been proposed (for example, Journal of the Institute of Electronics and Communication Engineers, Vol. 85/4, J68-D
No. 4, see Japanese Unexamined Patent Publication No. 58-215813).

FIG. 6 shows an example of this video image processing device in its original form.

Generally, this type of processing device has an input/output section (
1), input image memory (2A), and output image memory
(2B), a memory section (2) consisting of a data processing section (2B), and a data processing section (
3).

The input/output section +1) converts a video signal from, for example, a video camera (4) into a digital signal and converts it into a digital I! i image data, write this to the input image memory (2A), and
The processed W7L image data is read out from the output image memory (2B), D/A converted and returned to an analog video signal, and this is recorded on, for example, a VTR (51).
A monitor receiver (6) is supplied to enable the video image to be monitored.

Writing to and reading from the memory section (2) is performed in units of a group of images, that is, one field or one frame. Therefore, the input image memory (2A) and (2B
) each has a plurality of memories each having a capacity for 1 field or 1 frame of image data.

The data processing unit (3) uses a processor to read the image data stored in the input image memory (2) according to its program, performs various processing processes on it, and outputs the processed data to the output image memory (2B). ).

The processor of the data processing section (3) is composed of one or more processors, and the microprogram, which is the contents of the microprogram memory, can be replaced if the range of processing is to be further expanded. In this case, the microprogram is supplied to each processor from a program supply unit (generally a host computer) (7), and the microprogram is exchanged in response to a user's program exchange request (turning on a switch).

In the above-described image processing apparatus, there is a process called neighborhood processing in which when processing one pixel, data of a plurality of pixels around the one pixel is also used. An example of this processing is contour extraction. As a method for this contour extraction process, there is a method using a logical filter, which will be explained below.

This is a method in which, for example, 8-bit pixel data is converted into a z-value, and a 3×3 logical filter is applied to it to extract the outline of the image.

As a processing method, first, data of 3×3=9 pixels is binarized. That is, as shown in FIG. 7, eight pixels a1 to a3 . b1. b3 and CI-"CI is binarized to obtain a full size, b-muff, and C-muff, respectively.

Then, the logical sum of these nine binarized IIIi elements is calculated as follows.

'A"a maria furi a1 old; b muff Ub f C-C muff UC1 Subtract the binarized center value b f from the logical sum A, old, C obtained in this way. That is, AUIBU ( knee b) is determined and output as the center value b2 of the nine pixels.

Then, contour extraction is performed using this processing for each pixel over the entire screen.

The above method of contour extraction is performed by calculating the logical OR of the image data consisting of binarized rOJr'lJ. For example, if the original figure is a rectangle as shown in Fig. The original binarized value "1" shown with
By expanding the area (8) slightly (about 1 pixel) and removing the original ``1'' area (8) from this enlarged area, the area that has become ``1'' due to the enlargement process can be expanded. This method leaves only the outer peripheral pixel portion, that is, the portion (9) shown with right-slanted diagonal lines in FIG. 8, and uses this as the outline.

The binarization methods include the P-tile method, the mode method, the differential histogram method, and the discriminant analysis method, but here we will use the threshold values determined by these methods to
Perform value conversion.

By the way, when performing such neighborhood processing, one ii
Since data for eight pixels surrounding i-element is required, the method of manually inputting pixel data to the processor becomes a problem.

One method is to use delay circuits (10) and (11) of one horizontal period as shown in FIG.
Data DL1 from one horizontal period before A and data DL2 from two horizontal periods before A are obtained simultaneously, and these three pixel data arranged vertically on the screen are synchronized, and this is input to a processor, for example. 9 in the register section of the stage
There is a method of capturing and processing one pixel.

[Problem that the invention seeks to solve]

However, in the case of this method of manually inputting data using a delay circuit, data processing is delayed by the delay time, and real-time processing cannot be performed.

By the way, the following problem arises when performing real-time processing in this case. Zunawaji, for example, 3 as mentioned above.
In the case of neighborhood processing using a ×3 logical filter, it is necessary to use nine pixels of data to obtain an output for one pixel. Therefore, the data transfer rate on the input side must be nine times that on the output side.

Real-time processing is not possible simply by inputting data to a processor.

In view of the above points, the present invention enables real-time processing by making the data transfer rate on the input side and the output side substantially the same.

[Means for solving problems]

In this invention, processing is performed on one pixel data using surrounding pixel data, and a plurality of processors are provided for the above processing, and each pixel data is processed by one of the plurality of processors. To simultaneously supply data to multiple processors required for processing.

[Effect]

Input pixel data is simultaneously supplied to multiple processors that use this pixel data to perform neighborhood processing, so the data transfer rate when viewed from one processor is the same for human input and output, making real-time processing possible. It is what it is.

[Embodiment J] An example of the apparatus of this invention will be described below, taking as an example a case where it is applicable to the above-mentioned contour extraction as neighborhood processing.

First, in this example, the full screen data is divided into 2 as shown in Figure 2.
Divide into blocks B each having 0 horizontal lines, and each block B
Twenty processors are provided so that one processor is in charge of neighboring processing of one line of data.

In the case of the 3×3 processing described above as the neighborhood processing, one processor uses three lines of data to obtain a result for one line.

The input data to the processor for processing is that the image data is once stored in the input image memory, so it is read from this input image memory, but in this example, the image data is read from the input image memory. By devising the readout order, transferring one pixel data to the necessary processors at the same time, and using registers provided at the input stage of each processor, the data transfer rate on the input side can be adjusted to the output side. Make it possible to do the same.

FIG. 3 shows one block of 20 lines in the input image memory, in which lines Ll,
L2...Processor Pt for L20.

P2...P2O are made to correspond.

On the other hand, i! ! ! The order in which the l element data is read out from the human image memory is assumed to be read out in the vertical direction as shown by the arrow (12) in the figure. Therefore, in each block, 200 pixels in the vertical direction are successively transferred to the processor side.

At this time, the transferred data is simultaneously taken into the input register of the processor that requires the data.

For example, in the case of the contour extraction process using the 3×3 logical filter described above, consider the neighborhood process for the 10th image data of each line using the 9th to 11th lines in FIG. 3.

Now, the 9th and 10th pixel data d (t, 9), d (i, 10) (i=1°2) of lines L1 to L211
...20) to the processors P1 to P2o is completed, and the 11th pixel data d (
i.

11) is assumed to be transferred.

At this time, as shown in FIG. 1, the 11th pixel data d(1, 11) of line L1 is
, the 11th pixel data d(2,11) of line L2
is the processor Pt + P2 + Pi, and the input L3
The ll#th pixel d (3, 11) is the processor P2
, Pi, R4, the 111th pixel d(4
, 11) to processors P3, R4, Ps,...
In this way, the data are taken in via the input registers of each of the processors PI to P20.

The data taken into the input registers of each processor P1 to P20 is the 9th and 1st data of lines Ll-L20.
0th pixel data d(i, 9).

Together with d(i, 1G), the 10th center I! ! i
It is processed as nine pixel data necessary to calculate the output value of the element.

At this time, six of the pixel data of 9 (I!) used by the processor are the pixel data that were also used when calculating the output value of the previous ninth central pixel.

FIG. 4 shows the configuration of the input registers of each processor. This example is not only used for a 3 x 3 logical filter, but also an example where the structure is extended to enable neighborhood processing using a large amount of pixel data of s x 5-25 (1). It is.

That is, in the same figure, SR1, SR2...SRs
is a shift register provided corresponding to five horizontal lines, and the @ stages of the shift register for these five lines are buffer registers (21) and (22).

(23), (24), and (25) are provided. The input terminal for input pixel data is commonly supplied to these buffer registers.
The timing of clock supply to the register is controlled so that necessary pixel data is taken into a predetermined register.

Note that since this example deals with processing of a 3×3 logical filter, registers (24) and (25) and shift registers SR4 and SR5RI5 are not used.

When used as this 3×3 logic filter, three buffer registers (21),
When pixel data is stored in (22) and (23), the pixel data of these three (IA) is simultaneously transferred to the shift registers SRI for the first line, second line, and third line.

The data is transferred to SR2 and SR3.

When nine pixel data used by the processor are loaded into shift registers SR1, SR2, and SR3 for the first, second, and third lines,
The pixel data is transferred to the arithmetic unit of the processor and subjected to contour extraction processing as described above.

Transfer of data from the shift registers SR1, SR2, and SR3 to the arithmetic section of the processor is performed by instructions from a processing program of the control section of the processor. Processing using these nine pixel data is performed until the next data of the line that the processor is in charge of takes in the nine pixel data.

Taking the above-mentioned case as an example to further explain how data is taken into the input register of each processor, for example, the 11th pixel data d (2, 11) of line L2 is stored in the buffer register for the third line of the input register of processor P1. At the same time, it is taken into the buffer register (22) for the second line of the input register of processor P2, and further into the buffer register (21) for the first line of the input register of processor P3. .

Next, the 11th pixel data d (3°11) of line L3
is taken into the buffer register (23) for the third line of the processor P2, and also into the buffer register (22) for the second line of the processor P3, and further into the buffer register (22) for the first line of the processor P4. 21), it is taken in at the same time.

In this case, when the 11th three data of each line are newly taken into the register, the 8th three data that have already been used for processing are transferred to the next stage in the shift register and discarded. will be
Transfer waste is eliminated.

In the above processing, each processor stores three pieces of data in the shift registers SR1 and SR%.

Of course, the processing speed is sufficient to perform the above-described contour extraction processing before being transferred to the next stage in SR3.

Note that the formation of blocks for one screen, the order of reading within that block, and the method of loading into the input register vary depending on the processing, but the same data can be transferred to the necessary processors at the same time to increase the manual data transfer rate and output. The same goes for keeping the data transfer rates the same.

In addition, in the above example, when creating a block, the first line and the last line of the 20 lines will not be processed correctly (because the first line does not have one line before it, and the last line (This is because there is no peripheral data for one line after the last line.)
However, when dividing, for example, by overlapping each block by one line or more as shown in FIG. 5, the number of lines that cannot be determined correctly can be reduced.

It goes without saying that the input register section shown in FIG. 4 does not need to be provided within the processor, and may be provided in the preceding stage of the processor.

〔Effect of the invention〕

According to this invention, when performing neighborhood processing on one pixel data using peripheral data surrounding it, multiple processors are used and one data is transmitted to all of the multiple processors that require the data. By transferring data at the same time, the manual data transfer rate and the output data transfer rate become the same, which enables real-time processing.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of the main parts of an example of the device of this invention, FIGS. 2 and 3 are diagrams for explaining an example of how the device of this invention performs processing, and FIG. 4 is a diagram showing the components provided in each processor. FIG. 5 is a block diagram of an example of a human-powered register, FIG. 5 is a diagram showing an example of a dividing method when processing a divided screen, FIG. 6 is a block diagram of an example of an image processing device, and FIGS. 7 and 8 are Diagram 9 for explaining contour extraction processing as an example of neighborhood processing
The figure is a block diagram showing an example of input means of each processor when performing neighborhood processing. Pl, P2...P2O are processing processors, SRs
~SRs are shift registers. The same Hidemori Matsukuma's boyfriend 5°° Star II A's J blue diagram Figure 4 Fu' mouth, , 7 molecules IIφ Palace a shoulder leap Figure 5 Hi Deoi word name Me S King 14e In 7'0-77已a fig. B ◆ Life IIs, extraction reptile 3! Horo ♂ theory s 14 fig. 7 fig. 8 A fig. 9

Claims (1)

[Claims] One pixel data is processed using surrounding pixel data, and a plurality of processors are provided for the above processing, and each pixel data is processed by one of the plurality of processors. An image processing device that is configured to simultaneously supply data to multiple processors that require it.