JPS649574A - Video rate picture processor - Google Patents

Video rate picture processor

Info

Publication number
JPS649574A
JPS649574A JP16578887A JP16578887A JPS649574A JP S649574 A JPS649574 A JP S649574A JP 16578887 A JP16578887 A JP 16578887A JP 16578887 A JP16578887 A JP 16578887A JP S649574 A JPS649574 A JP S649574A
Authority
JP
Japan
Prior art keywords
arithmetic
control
bus
signal
prescribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16578887A
Other languages
Japanese (ja)
Other versions
JPH0823883B2 (en
Inventor
Tsugito Maruyama
Keiji Kahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62165788A priority Critical patent/JPH0823883B2/en
Publication of JPS649574A publication Critical patent/JPS649574A/en
Publication of JPH0823883B2 publication Critical patent/JPH0823883B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To freely change the content of arithmetic operation by using a CPU control so as to apply the selection of a frame memory and the constitution of an arithmetic module. CONSTITUTION:A control signal from a CPU is given to arithmetic control means 400-1-400-n and signal deciding means 420-1-420-n via a control bus 800. Signal decoding means 420-1-420-n built in the arithmetic control means decode and control signal and when the number designated by the control signal is coincident with the set number of the relevant arithmetic control means, the said arithmetic control means applies a prescribed arithmetic operation. If required, the storage means 300-1-300-n switch the bus by using the bus switching means 310-1-310-n and the data from a storage means designated by the control signal is given to a prescribed arithmetic control means via the 1st and 2nd input buses 900-1-900-n. An output bus changeover means 600 switches input/output and the resulting data is inputted and stored in the prescribed storage means via 1st and 2nd output buses 950-1, 950-2.
JP62165788A 1987-07-02 1987-07-02 Video rate image processor Expired - Lifetime JPH0823883B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165788A JPH0823883B2 (en) 1987-07-02 1987-07-02 Video rate image processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165788A JPH0823883B2 (en) 1987-07-02 1987-07-02 Video rate image processor

Publications (2)

Publication Number Publication Date
JPS649574A true JPS649574A (en) 1989-01-12
JPH0823883B2 JPH0823883B2 (en) 1996-03-06

Family

ID=15819011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165788A Expired - Lifetime JPH0823883B2 (en) 1987-07-02 1987-07-02 Video rate image processor

Country Status (1)

Country Link
JP (1) JPH0823883B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046356A (en) * 1988-09-28 1991-09-10 Kanzaki Paper Manufacturing Co., Ltd. Apparatus for determining water content of powder/granule
JPH05159042A (en) * 1991-12-02 1993-06-25 Sankyo Seiki Mfg Co Ltd Picture processor
JP2008084034A (en) * 2006-09-27 2008-04-10 Fujitsu Ltd Image processing apparatus
JP2009080797A (en) * 2007-08-15 2009-04-16 Nvidia Corp Conditional execute bit in graphics processor unit pipeline
JP2010033336A (en) * 2008-07-29 2010-02-12 Fujitsu Ltd Signal processor and signal processing method
US10685421B1 (en) 2017-04-27 2020-06-16 Apple Inc. Configurable convolution engine for interleaved channel data
US10747843B2 (en) 2016-06-30 2020-08-18 Apple Inc. Configurable convolution engine

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60159973A (en) * 1984-01-31 1985-08-21 Toshiba Corp Picture processing device
JPS61156363A (en) * 1984-12-27 1986-07-16 Toshiba Corp Data processing unit
JPS6214279A (en) * 1985-07-11 1987-01-22 Toshiba Eng Co Ltd Picture processing device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60159973A (en) * 1984-01-31 1985-08-21 Toshiba Corp Picture processing device
JPS61156363A (en) * 1984-12-27 1986-07-16 Toshiba Corp Data processing unit
JPS6214279A (en) * 1985-07-11 1987-01-22 Toshiba Eng Co Ltd Picture processing device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046356A (en) * 1988-09-28 1991-09-10 Kanzaki Paper Manufacturing Co., Ltd. Apparatus for determining water content of powder/granule
JPH05159042A (en) * 1991-12-02 1993-06-25 Sankyo Seiki Mfg Co Ltd Picture processor
JP2008084034A (en) * 2006-09-27 2008-04-10 Fujitsu Ltd Image processing apparatus
JP2009080797A (en) * 2007-08-15 2009-04-16 Nvidia Corp Conditional execute bit in graphics processor unit pipeline
JP2010033336A (en) * 2008-07-29 2010-02-12 Fujitsu Ltd Signal processor and signal processing method
US10747843B2 (en) 2016-06-30 2020-08-18 Apple Inc. Configurable convolution engine
US10685421B1 (en) 2017-04-27 2020-06-16 Apple Inc. Configurable convolution engine for interleaved channel data

Also Published As

Publication number Publication date
JPH0823883B2 (en) 1996-03-06

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