GB2016757A - Display Terminal - Google Patents

Display Terminal

Info

Publication number
GB2016757A
GB2016757A GB7904223A GB7904223A GB2016757A GB 2016757 A GB2016757 A GB 2016757A GB 7904223 A GB7904223 A GB 7904223A GB 7904223 A GB7904223 A GB 7904223A GB 2016757 A GB2016757 A GB 2016757A
Authority
GB
United Kingdom
Prior art keywords
cpu
memory
video display
dch
fetched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7904223A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of GB2016757A publication Critical patent/GB2016757A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A terminal display has a central processor unit (CPU) 21, a central memory 28, video display logic 35, video monitor 36, video display interface 34, and various bus drivers, transceivers, clock driver and clocks. The video display interface 34 includes means for making the CPU 21 think that an external I/O (input or output) device has made a data channel interrupt request (DCH. INT.), means for recognizing that the CPU 21 has acknowledged the DCH. INT., means for generating control signals to prevent the CPU 21 accessing memory 28, and means causing data to be fetched from memory 28 for display. In this system, data is fetched (read) out of memory 28 such that the video display logic 35 and monitor 36 sequentially share with the CPU 21 access to memory 28 and, in effect by diverting the CPU 21, the video display logic 35 steals, during each CPU cycle, a portion of the time of the CPU's normal access to memory 28. <IMAGE>
GB7904223A 1978-02-21 1979-02-07 Display Terminal Withdrawn GB2016757A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87937378A 1978-02-21 1978-02-21

Publications (1)

Publication Number Publication Date
GB2016757A true GB2016757A (en) 1979-09-26

Family

ID=25374023

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7904223A Withdrawn GB2016757A (en) 1978-02-21 1979-02-07 Display Terminal

Country Status (3)

Country Link
JP (1) JPS54163629A (en)
DE (1) DE2905658A1 (en)
GB (1) GB2016757A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0155499A2 (en) * 1984-02-20 1985-09-25 Ascii Corporation Display control unite
EP0522697A1 (en) * 1991-06-10 1993-01-13 International Business Machines Corporation Video memory interface to control processor access to video memory
CN114785445A (en) * 2022-06-20 2022-07-22 中国空气动力研究与发展中心低速空气动力研究所 Clock synchronization implementation method of wind tunnel pressure measurement system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0155499A2 (en) * 1984-02-20 1985-09-25 Ascii Corporation Display control unite
EP0155499B1 (en) * 1984-02-20 1993-01-07 Ascii Corporation Display control unite
EP0522697A1 (en) * 1991-06-10 1993-01-13 International Business Machines Corporation Video memory interface to control processor access to video memory
CN114785445A (en) * 2022-06-20 2022-07-22 中国空气动力研究与发展中心低速空气动力研究所 Clock synchronization implementation method of wind tunnel pressure measurement system

Also Published As

Publication number Publication date
DE2905658A1 (en) 1979-08-30
JPS54163629A (en) 1979-12-26

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)