JPS57130137A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57130137A
JPS57130137A JP1607981A JP1607981A JPS57130137A JP S57130137 A JPS57130137 A JP S57130137A JP 1607981 A JP1607981 A JP 1607981A JP 1607981 A JP1607981 A JP 1607981A JP S57130137 A JPS57130137 A JP S57130137A
Authority
JP
Japan
Prior art keywords
information
data
signal
processing
processing part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1607981A
Other languages
Japanese (ja)
Other versions
JPS6125180B2 (en
Inventor
Keiji Matsumoto
Tetsuji Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1607981A priority Critical patent/JPS57130137A/en
Publication of JPS57130137A publication Critical patent/JPS57130137A/en
Publication of JPS6125180B2 publication Critical patent/JPS6125180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To write commands and data independently of the state of peripheral processors, by providing one or more buffer registers, where information from address and data busses are stored, and signals which indicate the processing state for information from these busses. CONSTITUTION:The signal on an address bus 5, the signal on a data bus 6, and an information write signal 8 are inputted from a CPU 1 to a peripheral processor 2, and a command is written at a certain point. Since a signal 7 indicating whether the processing for information is in course of execution in an information processing part 4 of the device 2 or not is ''0'' still, a command is transferred to the processing part 4 to start the processing, and the signal 7 is set to ''1''. When data is written from the CPU 1, this data is stored in a buffer register 3 because of execution of the processing. When the processing of preceding data is terminated in the information processing part 4, the signal 7 is set to ''0'' to prepare for next information. This storage is executed for not only data but also information on the address bus.
JP1607981A 1981-02-05 1981-02-05 Data processor Granted JPS57130137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1607981A JPS57130137A (en) 1981-02-05 1981-02-05 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1607981A JPS57130137A (en) 1981-02-05 1981-02-05 Data processor

Publications (2)

Publication Number Publication Date
JPS57130137A true JPS57130137A (en) 1982-08-12
JPS6125180B2 JPS6125180B2 (en) 1986-06-14

Family

ID=11906542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1607981A Granted JPS57130137A (en) 1981-02-05 1981-02-05 Data processor

Country Status (1)

Country Link
JP (1) JPS57130137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6278639A (en) * 1985-10-02 1987-04-10 Oki Electric Ind Co Ltd Memory access system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5263624A (en) * 1975-11-20 1977-05-26 Matsushita Electric Ind Co Ltd Input controller

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5263624A (en) * 1975-11-20 1977-05-26 Matsushita Electric Ind Co Ltd Input controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6278639A (en) * 1985-10-02 1987-04-10 Oki Electric Ind Co Ltd Memory access system

Also Published As

Publication number Publication date
JPS6125180B2 (en) 1986-06-14

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