JPS57174724A - Error countermeasure controlling system for transfer data between computer devices - Google Patents

Error countermeasure controlling system for transfer data between computer devices

Info

Publication number
JPS57174724A
JPS57174724A JP56059858A JP5985881A JPS57174724A JP S57174724 A JPS57174724 A JP S57174724A JP 56059858 A JP56059858 A JP 56059858A JP 5985881 A JP5985881 A JP 5985881A JP S57174724 A JPS57174724 A JP S57174724A
Authority
JP
Japan
Prior art keywords
error countermeasure
error
signal line
data
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56059858A
Other languages
Japanese (ja)
Inventor
Osamu Takada
Hideo Uruga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56059858A priority Critical patent/JPS57174724A/en
Publication of JPS57174724A publication Critical patent/JPS57174724A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To carry out an error countermeasure at the receiver side in a uniform way and regardless of coexistence of a device that adds the error countermeasure information and a device that adds no error countermeasure information, by providing an error countermeasure signal line to decide the execution of an error countermeasure. CONSTITUTION:An error countermeasure signal line is provided to decide the execution of an error countermeasure. For instance, the signals of an address line 5, an address setter 8 and a storage device 10 are fed to an error countermeasure signal line 7 from the devices 2 and 3 having a function to add the error countermeasure information via an open collector gate 11. Thus the signal line 7 which is usually set at H is set at L, and at the same time the data added with the error countermeasure information is delivered to a data bus 6. Then the data on a data bus 6 is fed directly to a processor 1. In case an input is delivered from a device 4 that has no function to add the error countermeasure information, the data on the bus 6 is fed to a CPU16 via an error countermeasure device 12 provided in the processor 1.
JP56059858A 1981-04-22 1981-04-22 Error countermeasure controlling system for transfer data between computer devices Pending JPS57174724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56059858A JPS57174724A (en) 1981-04-22 1981-04-22 Error countermeasure controlling system for transfer data between computer devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56059858A JPS57174724A (en) 1981-04-22 1981-04-22 Error countermeasure controlling system for transfer data between computer devices

Publications (1)

Publication Number Publication Date
JPS57174724A true JPS57174724A (en) 1982-10-27

Family

ID=13125293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56059858A Pending JPS57174724A (en) 1981-04-22 1981-04-22 Error countermeasure controlling system for transfer data between computer devices

Country Status (1)

Country Link
JP (1) JPS57174724A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175251U (en) * 1986-11-21 1988-11-14
JPH0216636A (en) * 1988-03-31 1990-01-19 Wang Lab Inc Parity inspector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175251U (en) * 1986-11-21 1988-11-14
JPH0216636A (en) * 1988-03-31 1990-01-19 Wang Lab Inc Parity inspector

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