JPS5714931A - Interruption controlling system - Google Patents
Interruption controlling systemInfo
- Publication number
- JPS5714931A JPS5714931A JP9009680A JP9009680A JPS5714931A JP S5714931 A JPS5714931 A JP S5714931A JP 9009680 A JP9009680 A JP 9009680A JP 9009680 A JP9009680 A JP 9009680A JP S5714931 A JPS5714931 A JP S5714931A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- input
- signal
- significant
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Abstract
PURPOSE:To realize a response to the interruption request of an input/output device with an optional priority and at the same time carry out the processes of many interruption factors, by providing the signal lines for read of interruption requests. CONSTITUTION:When an interruption request occurs from input/output devices 2-1-2-n, a CPU1 detects this request via a signal line 4 and delivers the interruption reception signal to a signal line 5 when the reception is possible. On the contrary, an input/output device makes each proper bit position significant after detecting the reception of interruption and transmits the bit position to the line 4. The CPU1 reads the data of signal line to identify the input/output device that gave an interrpution request. When detecting plural significant bits, the CPU performs a decision of priority to one of input/output devices and at the same time makes a signal line significant. In response to the significant signal of the line 6, the input/ output device received a priority transmits the significant signal to a signal line 3. The CPU1 reads the data of the line 3 to start an interruption process in accordance with the interruption factor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9009680A JPS5714931A (en) | 1980-06-30 | 1980-06-30 | Interruption controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9009680A JPS5714931A (en) | 1980-06-30 | 1980-06-30 | Interruption controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5714931A true JPS5714931A (en) | 1982-01-26 |
Family
ID=13988982
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9009680A Pending JPS5714931A (en) | 1980-06-30 | 1980-06-30 | Interruption controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5714931A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60152636A (en) * | 1984-01-23 | 1985-08-10 | Nippon Furnace Kogyo Kaisha Ltd | Soaking furnace |
JPH031261A (en) * | 1989-05-30 | 1991-01-07 | Oki Electric Ind Co Ltd | Interruption informing system |
-
1980
- 1980-06-30 JP JP9009680A patent/JPS5714931A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60152636A (en) * | 1984-01-23 | 1985-08-10 | Nippon Furnace Kogyo Kaisha Ltd | Soaking furnace |
JPH0514011B2 (en) * | 1984-01-23 | 1993-02-24 | Nippon Furnace Kogyo Kk | |
JPH031261A (en) * | 1989-05-30 | 1991-01-07 | Oki Electric Ind Co Ltd | Interruption informing system |
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