JPS56121124A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS56121124A
JPS56121124A JP2459380A JP2459380A JPS56121124A JP S56121124 A JPS56121124 A JP S56121124A JP 2459380 A JP2459380 A JP 2459380A JP 2459380 A JP2459380 A JP 2459380A JP S56121124 A JPS56121124 A JP S56121124A
Authority
JP
Japan
Prior art keywords
error
signal
channel device
signal line
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2459380A
Other languages
Japanese (ja)
Inventor
Tomohito Shibata
Noboru Yamamoto
Tomoharu Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2459380A priority Critical patent/JPS56121124A/en
Publication of JPS56121124A publication Critical patent/JPS56121124A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To shorten an error processing time by providing an error signal line between a channel device and I/O controller and by informating the channel device of error detection via this signal line. CONSTITUTION:Data D from signal line (d) of the channel device is set in register 6 in the I/O controller with white signal W from signal line (a). Next, detecting circuit 8, when detecting a parity error of data in register 6, outputs error signal E. Since this signal E sets FF12, error signal AE is sent via error signal line (f) to inform the channel device of the error, and gate 7 is closed to inhibit the transmission of data. The channel device completes the data transfer procedure with this signal AE. Thus, error signal AE is only sent out on the error detection, so that the error processing time is shortened.
JP2459380A 1980-02-28 1980-02-28 Bus control system Pending JPS56121124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2459380A JPS56121124A (en) 1980-02-28 1980-02-28 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2459380A JPS56121124A (en) 1980-02-28 1980-02-28 Bus control system

Publications (1)

Publication Number Publication Date
JPS56121124A true JPS56121124A (en) 1981-09-22

Family

ID=12142448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2459380A Pending JPS56121124A (en) 1980-02-28 1980-02-28 Bus control system

Country Status (1)

Country Link
JP (1) JPS56121124A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120458A (en) * 1983-12-05 1985-06-27 Nec Corp Data transferring device
US4864531A (en) * 1983-06-03 1989-09-05 La Telemecanique Electrique Error control apparatus using restore memory for recovering from parity discordances in transmissions between controller and real-time I/O devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864531A (en) * 1983-06-03 1989-09-05 La Telemecanique Electrique Error control apparatus using restore memory for recovering from parity discordances in transmissions between controller and real-time I/O devices
JPS60120458A (en) * 1983-12-05 1985-06-27 Nec Corp Data transferring device

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