JPS5736330A - Connection circuit for additional device - Google Patents

Connection circuit for additional device

Info

Publication number
JPS5736330A
JPS5736330A JP11128180A JP11128180A JPS5736330A JP S5736330 A JPS5736330 A JP S5736330A JP 11128180 A JP11128180 A JP 11128180A JP 11128180 A JP11128180 A JP 11128180A JP S5736330 A JPS5736330 A JP S5736330A
Authority
JP
Japan
Prior art keywords
switch
circuit
main device
additional device
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11128180A
Other languages
Japanese (ja)
Inventor
Jo Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11128180A priority Critical patent/JPS5736330A/en
Publication of JPS5736330A publication Critical patent/JPS5736330A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To connect an external additional device to a main device through remaining in connecting the operation electric source of main device, by holding the action of the main device temporally with an operation switch and controlling a gate function circuit with another switch. CONSTITUTION:When a switch SW2 provided to a switch circuit 104 is turned on during the operation of a main device 101, a hold request signal is outputted from the circuit 104. After closing respective gates NA1-NA3 of a signal transmission/reception part 102A by a control signal outputted from a switch circuit 103, each signal line of the transmission/reception part 102A is connected to prescribed signal line of the device 101. Since the device 101 has been already held by the circuit 104, no influence is given by the connection of an additional device 102. When a switch SW2 is turned off after turning on the switch SW1, the hold status of the device 101 is released and the processing action is restarted.
JP11128180A 1980-08-13 1980-08-13 Connection circuit for additional device Pending JPS5736330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11128180A JPS5736330A (en) 1980-08-13 1980-08-13 Connection circuit for additional device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11128180A JPS5736330A (en) 1980-08-13 1980-08-13 Connection circuit for additional device

Publications (1)

Publication Number Publication Date
JPS5736330A true JPS5736330A (en) 1982-02-27

Family

ID=14557244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11128180A Pending JPS5736330A (en) 1980-08-13 1980-08-13 Connection circuit for additional device

Country Status (1)

Country Link
JP (1) JPS5736330A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0254456A2 (en) * 1986-07-21 1988-01-27 AT&T Corp. Apparatus for controlled removal and insertion of circuit modules
EP0426134A2 (en) * 1989-10-31 1991-05-08 Kabushiki Kaisha Toshiba Method and system for holding bus at insert/extract of IC card in computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0254456A2 (en) * 1986-07-21 1988-01-27 AT&T Corp. Apparatus for controlled removal and insertion of circuit modules
EP0426134A2 (en) * 1989-10-31 1991-05-08 Kabushiki Kaisha Toshiba Method and system for holding bus at insert/extract of IC card in computer

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