JPS577647A - Fault processing system - Google Patents

Fault processing system

Info

Publication number
JPS577647A
JPS577647A JP8161980A JP8161980A JPS577647A JP S577647 A JPS577647 A JP S577647A JP 8161980 A JP8161980 A JP 8161980A JP 8161980 A JP8161980 A JP 8161980A JP S577647 A JPS577647 A JP S577647A
Authority
JP
Japan
Prior art keywords
data
circuit
output
gate
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8161980A
Other languages
Japanese (ja)
Inventor
Rikuro Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8161980A priority Critical patent/JPS577647A/en
Publication of JPS577647A publication Critical patent/JPS577647A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/14—Arrangements for detecting or preventing errors in the information received by using return channel in which the signals are sent back to the transmitter to be checked ; echo systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To continue data transfer by selecting a data bus when an error is detected in a data buffer (register). CONSTITUTION:A transmitted signal from a channel is received by a receiving circuit 3 and further sent to a delay circuit 5 and a gate. Data is sent to a bus checking circuit 11 and a data selector 13 through a data buffer 9 and a bus 1. Data in the buffer 9 is checked by a checking circuit 15, which when finding it to be normal, generates an output 0; and then a selector 14 selects the data in the buffer and the condition of the gate 21 is satisfied to return the received signal to the channel via a line 28. When the output of the circuit 15 is abnormal, data on the bus is selected by the selector 13 and when the output of the circuit is normal and 0, a gate 24 is conditioned to output the received signal to the line 28, so that a counter goes up. If the output of the circuit is abnormal, a gate 25 is conditioned and a fault FF is put in operation.
JP8161980A 1980-06-17 1980-06-17 Fault processing system Pending JPS577647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8161980A JPS577647A (en) 1980-06-17 1980-06-17 Fault processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8161980A JPS577647A (en) 1980-06-17 1980-06-17 Fault processing system

Publications (1)

Publication Number Publication Date
JPS577647A true JPS577647A (en) 1982-01-14

Family

ID=13751336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8161980A Pending JPS577647A (en) 1980-06-17 1980-06-17 Fault processing system

Country Status (1)

Country Link
JP (1) JPS577647A (en)

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