JPS5760422A - Data transfer controlling system - Google Patents
Data transfer controlling systemInfo
- Publication number
- JPS5760422A JPS5760422A JP55135194A JP13519480A JPS5760422A JP S5760422 A JPS5760422 A JP S5760422A JP 55135194 A JP55135194 A JP 55135194A JP 13519480 A JP13519480 A JP 13519480A JP S5760422 A JPS5760422 A JP S5760422A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- decoder
- selecting
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
Abstract
PURPOSE:To transfer data by a simple interface, by utilizing a data transfer controlling signal, and sending out a selecting signal 2 times to an I/O controller from a microprocessor. CONSTITUTION:A microprocessor (muPC) 11 sends data and a selecting signal to a printed circuit substrate 12 through a data signal line 20 and a control signal line 21 at the first time in order to operate an I/O controller (CT) 15. A decoder 16 of the substrate 12 decodes the selecting signal, outputs a signal, the data is stored in a data register 17, and at the same time, a flip-flop (FF) 18 is set. When the muPC11 sends the second selecting signal to the decoder 16, the decoder 16 outputs a signal by said signal, therefore, signals from the FF18 and the decoder 16 are supplied to an AND gate 19. A write signal relating to the I/O CT15 is provided from the gate 19, and the data stored in the register 17 is inputted to the I/O CT15.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55135194A JPS5760422A (en) | 1980-09-30 | 1980-09-30 | Data transfer controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55135194A JPS5760422A (en) | 1980-09-30 | 1980-09-30 | Data transfer controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5760422A true JPS5760422A (en) | 1982-04-12 |
Family
ID=15146034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55135194A Pending JPS5760422A (en) | 1980-09-30 | 1980-09-30 | Data transfer controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5760422A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6068568A (en) * | 1996-12-12 | 2000-05-30 | Tsubakimoto Chain Co. | Silent chain |
WO2009040915A1 (en) | 2007-09-27 | 2009-04-02 | Daido Kogyo Co., Ltd. | Link chain |
-
1980
- 1980-09-30 JP JP55135194A patent/JPS5760422A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6068568A (en) * | 1996-12-12 | 2000-05-30 | Tsubakimoto Chain Co. | Silent chain |
WO2009040915A1 (en) | 2007-09-27 | 2009-04-02 | Daido Kogyo Co., Ltd. | Link chain |
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