JPS5748125A - Channel device - Google Patents

Channel device

Info

Publication number
JPS5748125A
JPS5748125A JP12326380A JP12326380A JPS5748125A JP S5748125 A JPS5748125 A JP S5748125A JP 12326380 A JP12326380 A JP 12326380A JP 12326380 A JP12326380 A JP 12326380A JP S5748125 A JPS5748125 A JP S5748125A
Authority
JP
Japan
Prior art keywords
chcont
cpu
bussw
dbus
data bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12326380A
Other languages
Japanese (ja)
Inventor
Fumio Oki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12326380A priority Critical patent/JPS5748125A/en
Publication of JPS5748125A publication Critical patent/JPS5748125A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To make it unnecessary to adjust the right of using a data bus, by detaching a part of the data bus from a system. CONSTITUTION:A CPU and a main memory MM are connected by a data bus DBUS, and also a local memory LM, an input/output port IO and a channel controller CHCONT are connected to a part of detached DBUS by a bus switch BUSSW. Since the DBUS is usually turned off, the CPU and the CHCONT can continue the operation without being conscious of each other. In case when reading and writing are executed from the CPU to the LM, the IO, etc., the CHCONT is made a waiting state by generating a CHREQ signal for turning on the BUSSW. In the waiting state, the CHCONT makes an address output a high impedance, stops a control signal to the IO and the LM, too, and after that turns on the BUSSW, therefore, the CPU executes read and write operations from the LM, etc.
JP12326380A 1980-09-05 1980-09-05 Channel device Pending JPS5748125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12326380A JPS5748125A (en) 1980-09-05 1980-09-05 Channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12326380A JPS5748125A (en) 1980-09-05 1980-09-05 Channel device

Publications (1)

Publication Number Publication Date
JPS5748125A true JPS5748125A (en) 1982-03-19

Family

ID=14856230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12326380A Pending JPS5748125A (en) 1980-09-05 1980-09-05 Channel device

Country Status (1)

Country Link
JP (1) JPS5748125A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02277155A (en) * 1989-04-19 1990-11-13 Pfu Ltd Bus controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02277155A (en) * 1989-04-19 1990-11-13 Pfu Ltd Bus controller

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