JPH02277155A - Bus controller - Google Patents

Abstract

PURPOSE:To validate an output with a delay approximately equal to the delay time of a gate and to attain the working of a bus controller at a high speed by validating a bus request signal via a 1st controller. CONSTITUTION:When a main controller 10 outputs a request signal 14, the output of a control circuit 25 is invalidated and an access grant signal 36 outputted from a bus arbiter 20 is also invalidated. This state lasts until the controller 10 finishes the use of a bus. When the controller 10 is through with use of the bus, the output of the circuit 25 is validated and the signal 36 is also validated. However the signal 36 is never validated to a 1st controller 30 unless the other input of an AND circuit 26, i.e., a bus request signal 34 is valid. Under such conditions, the output of the circuit 26 is validated with a delay approximately equal to the delay time of a gate if the controller 30 validates the signal 34. Thus the signal 36 is immediately inputted to the controller 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus management device that interconnects a plurality of modules via the same number of buses and manages the use of the buses of each module.

[Conventional technology]

FIG. 4 is a diagram showing an example of a system including this type of bus management device.

The MPU 100 which is the main control device and the bus arbiter 200 provided in the bus management device are connected by an MPU bus 120, the line control device 300 which is the first control device and the bus arbiter 200 are connected by an LSI bus 320, and the bus arbiter 200 which is the first control device is connected by an LSI bus 320. The RAM 400, which is a control device, and the bus arbiter 200 are connected by a RAM bus 420. Also, MPU10
Between 0 bus arbiter 200 and MPU 100
The line control LSI 300 and the bus arbiter 200 are connected to each other so that a bus request signal 140 requesting the use of the bus and an access permission signal 160 in response to the request signal are exchanged.
The connection is such that a bus request signal 340 requesting the use of the bus from the 0 side and an access permission signal 360 as a response thereto are exchanged.

MPU 100 can access line control LSI 300 and RAM 400 via the bus. M
PU100 is line control LSI300 or RAM400
When accessing, first, the bus request signal 140 is enabled, and when the access permission signal 160 is returned, the access is started as indicated by the broken line A or C.

The line control LSI 300 can access the RAM 400 via the bus.0 When the line control LSI 300 accesses the RAM 40G, the bus request signal 34
0 is enabled and when the access permission signal 360 is returned, access is started as shown by line B.

The bus arbiter 200 samples bus request signals from each module in synchronization with the basic clock, and if there are bus request signals from two or more modules at the same time, determines their priorities and directs them to the module with the highest priority. Issue an access permission signal.

For example, if the bus request signals 140 and 340 are input from the MPU 100 and the line control LSI 300 at the same time, the access permission signal 16 for Mputoo with a high priority
0 is enabled and the access permission signal 360 to the line control LSI 300 is sent after using the NPUloo bus.
Enable.

As for the movement of the entire system, the MPU 100 controls the line
A case in which data is sent out to the outside of the system via the SI 300 and a case in which data is received from outside the system will be explained. When transmitting data, MPtllOO first acquires the right to use the bus in the order described above, and issues commands to the line control LSI 300 via the buses 120 and 320.
00 similarly acquires the right to use the bus in the aforementioned order and transfers the data in the RAM 400 to the buses 420 and 32.
0 line control LSI 3 that reads out and sends out to the outside via 0
When 00 starts receiving data, it first acquires the right to use the bus in the above order, and transfers the received data to buses 320 and 42.
0 to the RAM 400.

[Problem to be solved by the invention]

As mentioned above, the bus acquisition 200 sequentially performs the process from sampling the bus request signal to determining the priority and outputting the access permission signal in synchronization with the basic clock. This clock is usually about 10 MHz. The entire process takes several clocks. Therefore, in a system that requires high-speed operation, this time becomes a bottleneck and the overall operating speed is suppressed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to propose a bus management device that can perform processing from generation of a bus request signal to output of a permission signal faster than before.

[Means to solve the problem]

FIG. 1 is a principle block diagram showing the bus management device of the present invention. In FIG. , and a second controller 40 that performs slave operation.
, 30, 40 the same number of buses! 2, 32, 42 and become master modules 10, 3.
In a bus management device equipped with a bus arbiter 20 that arbitrates bus request signals 14 and 34 from 0 and sends access permission signals 18 and 36 to each of the bus request signals 14 and 34 from the main controller and device 10, 1 control device 30
a bus request signal 34 of the main controller 10 is connected to an input; an output is connected to a bus request signal input for the first controller 30 of the bus arbiter 20; is valid and the bus request signal 34 of the first control device 30 is invalid, and the control f# times 125 is valid when the bus request signal 14 of the main control device 10 is invalid. , the bus request signal 34 of the first control device 30 and the access grant signal 36 for the first control device 30 of the bus arbiter 20 are connected to inputs, and the output is connected to the access permission signal 36 of the first control device 30. The device is characterized in that it includes an AND circuit 26 connected to the permission signal input.

[For production]

When the main controller 10 outputs a bus request signal, the control circuit 2
The output of 5 is invalid and therefore the access permission signal 3 for the first control device 30 output by the bus arbiter 20
6 becomes invalid, and this state of the access permission signal 36 persists until the main controller IO finishes using the bus. When the main controller 10 finishes using the bus, the output of the control circuit 25 becomes valid, and therefore the access permission signal 36 also becomes valid. However, unless the other input of the AND circuit 26, that is, the bus request signal 34 of the first control device 30, is valid, the output of the AND circuit 26 is not valid, and therefore, for the first control device 30, the access permission signal is not valid. is not.

If the first control device 30 validates the bus request signal 34 in this state, the output of the AND circuit 26 becomes valid with a delay equivalent to the gate delay time, and the access permission signal is immediately input to the first control device 30. be done.

〔Example〕

FIG. 2 is a circuit block diagram showing one embodiment of the bus management device according to the present invention.

Components that are the same as those in FIG. 4 are given the same reference numerals, and some explanations thereof will be omitted.

The bus request signal 140 from the MPU 100 is input to the bus arbiter 200 as in FIG.
A flip-flop 250, an OR gate 252, an AND gate 254, and an inverter 2 realize (FIG. 1)
58 and 258.

Unlike the bus request signal 340 (FIG. 4), the bus request signal 342 from the line control LSI is input to the aforementioned circuit, and its output, that is, the output of the flip-flop 250, is sent to the bus arbiter 2.
00 as a bus request signal from the line control LSI 300. From the bus arbiter 200 to the line control LS [3
The access permission signal 362 output towards 00 is 36
0 (FIG. 4), the bus request signal 342 of the 0 line control LSI 300, which is input to the AND gate 260 and whose output is input as an access permission signal to the line control LSI 300, is also connected to the other input of the AND gate 280. ing.

The detailed configuration of the circuit composed of flip-flop 250, OR gate 252, AND gate 254, and inverters 256 and 258 will be described. MPU
The bus request signal 140 from 100 is logically inverted by an inverter 258 and input to one of the inputs of an OR gate 252, and is also connected to one of the inputs of an AND gate 254. The other input of the AND gate 254 is inputted with a bus request signal 342 from the i1LsI 300 that is logically inverted by an inverter 256.
A reset signal is connected to the other input of the R gate 252. O for the set input of flip-flop 250
The output of the R gate 252 is connected to the reset input, and the output of the AND gate 254 is connected to the reset input.

FIG. 3 is a diagram for explaining the operation of the apparatus shown in FIG. 2. The states of the signals at the locations indicated by symbols AF in FIG. 2 are shown in (A) to (F)i, respectively.

The operation of one embodiment of the present invention will be described below with reference to FIGS. 2 and 3. Initially, reset signal A is H.
Since the output of the OR gate 252 becomes the H level, the output B of the flip-flop 250 becomes the H level and is input to the bus arbiter 200 as a bus request signal from the line control LSI 300. At this time, MP is still
Since the bus request signal 140 (column (F)) from U100 is not at the H level, the bus arbiter 200 sets the access permission signal 362 to the line control LS 1300 at the H level ((C)!>. In this state Line control jLsI
300 sets the bus request signal 342 to H level (D
) column), the output of the AND gate 260 immediately becomes H level (column (E)), and access to the line control LSI 300 is permitted. ′: Returned as a number. After that, when the MPU 100 sets the access request signal 140 to H level (column (F)), it is input to one side of the AND gate 254.
Bus request signal 3 while line control LSI 300 is using the bus
As long as 42 is at H level, the other input of AND gate 254 is at L level, so the output of AND gate 254 does not change, and therefore the output of flip-flop 250 also remains at H level (column (B)). After that, when the line control LSI 300 finishes using the bus and the bus request signal 342 goes to L level (column (D)), the AN immediately
The output of the D gate becomes L level (column (E)) and A
The output of the ND gate 254 becomes H level, the flip-flop 250 is reset, and its output becomes L level (column (B)). Therefore, after that, the bus arbiter 20
0 makes the output 362 L level (column (C)),
By setting the access permission signal 180 (not shown in FIG. 3) to NPUloo to H level, NPUlo
When bus request signal 140 becomes L level after MPU 100 finishes using the bus (column (F)), the output of inverter 258 becomes H level, and the output of OR gate 252 becomes H level. It becomes H level, the flip-flop 250 is set, and returns to the state immediately after input of the reset signal.

Generally, the MPU 100 accesses the line control LSI 300 for temporary purposes such as initializing, starting, and stopping the LSI, and normally the MPU 100 accesses the LSI bus 320.
Since the output of flip-flop 250 is usually kept at H level, line control LSI 300 can operate at high speed without being affected by the operating time of bus arbiter 200.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a bus management device that can reduce the time from the input of a bus request signal to the output of an access permission signal to about the delay time of a gate.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the principle configuration of the present invention, Fig. 2 is a circuit block diagram showing an embodiment of the invention, Fig. 3 is a flowchart showing the operation of the circuit shown in Fig. 2, and Fig. 4 is a conventional FIG. 3 is a diagram showing a bus management circuit of. In the figure, 12, 32, 42, 120, 320, 420
...Bus, 14, 34, 140, 340, 3
42... bus request signal, 16, 36, 160,
360, 362... Access permission signal.

Claims (1)

[Claims] 1. Includes a main control device (10) that performs master operation, a first control device (30) that performs master and slave operations, and a second control device (40) that performs slave operation. A plurality of modules (10, 30, 40) are connected to each other via the same number of buses (12, 32, 42), and a bus request signal (
14, 34) and sends an access permission signal (16, 36) to each bus management device, the bus request signal (14) of the main control device (10) and The first
a bus request signal (34) of a control device (30) of the bus arbiter (20) is connected to an input, and an output is connected to a bus request signal input for the first control device (30) of the bus arbiter (20);
Its output is the bus request signal (14) of the main controller (10).
) is valid and the bus request signal (34) of the first control device (30) is invalid, and becomes invalid when the bus request signal (14) of the main control device (10) is invalid. a control circuit (25) that is enabled, a bus request signal (34) of the first control device (30) and an access grant signal (36) for the first control device (30) of the bus arbiter (20). ) and an AND circuit (26) connected to the input and the output connected to the access permission signal input of the first control device (30).