JPH02222059A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To improve the throughput of a multiprocessor system by preparing an arbiter device to apply a shared memory enabling signal and using a clock signal/delayed clock signal generating circuit and a circuit which secures an OR of both clock signals and an AND with an access enabling control signal to form a scanning circuit. CONSTITUTION:A clock signal of a timer 31 having a prescribed cycle is divided into two pieces by a scanning circuit 12, and one of these two signals is inputted to a delay circuit 32. The clock signal delayed by the circuit 32 by a prescribed time T is inputted to an OR circuit 33 to secure an OR with the previous clock signal. The output of the circuit 33 is inputted to an AND circuit 34 which is opened and closed by an access enabling control signal received from a controller 14 of an arbiter device 15. Thus a shared memory enabling signal can be applied to an acceptance control circuit corresponding to an arithmetic processor that transmitted the shared memory request signal having the highest priority at the relevant time point in accordance with the priority given to the shared memory request signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system having a single shared memory.

[Fukuroki technology]

FIG. 8 is a block diagram showing a conventional multiprocessor system disclosed in, for example, Japanese Unexamined Patent Publication No. 52-103935.
C and 3a to 3C are the arithmetic processing device 1a-1, respectively.
A read-only memory (hereinafter referred to as RO) provided corresponding to c.
M) and read/write memory (hereinafter referred to as RAM); 4 is a shared memory having blocks that can be shared by the arithmetic processing units 1a to IC; 5a to 4;
Reference numeral 5c denotes an admission control circuit that receives a shared memory request signal outputted when the arithmetic processing unit 1a-IC wants to use the shared memory 4. Each of the admission control circuits 5a to 5c is configured in an AND gate manner, and the conditions thereof are Each signal is derived based on the establishment of the condition. Reference numeral 6 denotes a scanning circuit that cyclically issues a shared memory permission signal to each of the reception control circuits 5a to 5C, and this scanning circuit is formed by interconnecting edge trigger type flip-flops 21 to 24, as shown in FIG. It consists of a clock-shifted ring counter. Also, 7a-7c
is provided corresponding to each arithmetic processing device 1a to 1c, and when the arithmetic processing device 1a to IC use the shared memory 4,
Data registers 8a to 8c that store predetermined data are address registers that store address signals for specifying which block of the shared memory 4 the data stored in the data registers 7a to 7c should be input to. . 10a to 10c send address signals to address register 8.
Address buses lla to llc are data buses for sending data to data registers 7a to 7c.

Further, the reception control circuits 5a to 5C, the data register 7
A to 7C and address registers 8a to 8C constitute an input/output port.

Next, the operation will be explained. First, which arithmetic processing device 1
A case will be described in which neither a to IC access the shared memory 4. In this case, the scanning circuit 6 sends a high-speed cyclic shared memory permission signal to the reception control circuits 5a to 5.
I am sending it to C. However, each arithmetic processing unit 1a to IC
are ROMs 2a to 2c and RAMs 3a to 2c provided corresponding to the processing units ff1la to IC, respectively.
3c to address buses 10a to 10c.
and data buses lla to llc to execute predetermined arithmetic processing.

Therefore, the arithmetic processing units 1a to IC do not need to use the shared memory 4, and the scanning circuit 6 receives the above-mentioned cyclic shared memory permission signal without outputting the shared memory request signal to the admission control circuits 5a to 5C. This will only continue to occur.

Next, a case where a plurality of arithmetic processing units 1a to IC access the shared memo I74 will be described. For example, when the arithmetic processing unit 1b is performing arithmetic processing using the ROM2b and RAM3b and a situation arises in which it is desired to write to the shared memory 4, the arithmetic processing unit 1c also writes to the shared memory 4 at the same time. Suppose that a situation arises. in this case,
Each of the arithmetic processing units 1b and lc independently issues a shared memory request signal to the corresponding reception control circuits 5b and 5C, and at the same time, the data registers 7b and 7C
and address registers 8b and 8C via data buses llb and llc and address buses 10b and 10c, respectively.

The data signals and address signals sent from the arithmetic processing unit 1b and the IC in this way are independently held in the data registers 7b and 7C and the address registers 8b and 8C, and are sent from the scanning circuit 6 to the reception control circuit 5b.
and waits for a shared memory permission signal to be input to 5C.

Here, this scanning circuit 6 is initialized by an initial setting signal, and only the final stage flip-flop 24 is set to "1", and the other flip-flops 21 to 23 are reset to "0". When the signal is supplied, the flip-flop 24 is reset at the first rising edge of the clock signal, and at the same time, the first-stage flip-flop 21 is set.Therefore, the output A changes to "0" and the output A becomes "L". ”.When the next clock signal is applied, the flip-flop 21 is activated at the rising edge.
is reset and the flip-flop 22 is set. Therefore, the output A changes to 0'' and the output B becomes 1''. Thereafter, each time a clock signal is input, the indirect flip-flops 21 to 24 are set in the same manner.
The scanning circuit 6 outputs a cyclic signal from each output AS-D as a shared memory permission signal. FIG. 10 is a time chart showing the time relationship of each signal. When the input of the clock signal stops, the 6-scanning circuit 6 stops generating the cyclic shared memory permission signal.

When the shared memory permission signal is issued from the scanning circuit 6, one of the admission control circuits 5b and 5c waiting for the input thereof, to which the shared memory permission signal was inputted first; For example, 5b holds the shared memory enable signal and stops the clock signal of the scanning circuit 6 to prevent cyclic operation.

Further, the reception control circuit 5b sends an access permission signal to the data register 7b and the address register 8b on the condition that the shared memory request signal from the arithmetic processing unit 1b and the shared memory permission signal from the scanning circuit 6 are input. Data register 7b that received this access permission signal
The address register 8b manually inputs the data signal and address signal held as described above to the shared memory 4 to perform a write operation. After that, when the write operation is completed, the reception control circuit 5b sends an access end signal indicating completion of the write to the arithmetic processing unit 1b and the scanning circuit 6. In response to this access end signal, the scanning circuit 6 restarts the clock signal, restarts the cyclic operation of the shared memory permission signal that had been blocked by the reception control circuit 5b, and re-inputs the shared memory from each arithmetic processing unit 1a to 1c. Wait for a request signal to be sent. As mentioned above, since the arithmetic processing unit IC has already sent out the shared memory request signal, the arithmetic processing unit IC continues to write to the shared memory 4 in the same manner as the arithmetic processing unit 1b writes to the shared memory 4. Write to 4.

Although writing has been described above, the shared memory 4 is accessed using the same procedure for reading.

[Problem to be solved by the invention]

Since the conventional multiprocessor system is configured as described above, even if it becomes necessary to access the shared memory 4 with priority over other processing units 1a to 1C, the processing units 1a to 1C are Shared memory 4 with priority
There is no guarantee that the access right will be granted, and the scanning circuit 6 that cyclically generates the shared memory permission signal
The ring counter that makes up the ring counter will stop operating if all of its flip-flops 21 to 24 are reset to 0'' due to some reason, and the operation will continue until the initial setting signal is input again. Since the system was not repaired, there were problems such as poor system reliability.

This invention was made in order to solve the above-mentioned problems, and it is possible to access the shared memory according to its priority, and the cyclic shared memory permission signal generation operation is stopped unnecessarily. The purpose of the present invention is to obtain a multiprocessor system equipped with a scanning circuit without a scanning circuit.

[Means to solve the problem]

A multiprocessor system according to the present invention includes a control device that provides a shared memory permission signal to an admission control circuit corresponding to an arithmetic processing unit that has issued a shared memory request signal according to a priority added to the shared memory request signal. In addition to adding an arbiter device having a scanning circuit, a clock means for generating a clock signal, a delay means for generating a delayed clock from the clock signal, an OR means for ORing both signals, and an output of the OR means. and an access permission control signal from the control device.

[For production]

The scanning circuit according to the present invention divides the clock signal generated by the clock means into two, and inputs one as is and the other after giving a predetermined delay by the delay means to the OR means, and calculates the logical sum of the two. The arbiter device logically ANDs the output of the OR means and the access permission control signal from the control device and outputs it as a cyclic shared memory permission signal. When a memory request signal is received, the reception control circuit associated with the arithmetic processing unit that has sent out the shared memory request signal with the highest priority at that time, according to the priority added to the shared memory request signal, Provides a shared memory enable signal generated by the circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2a to 2C are ROM, 3a to 3C are RAM
, 4 is a shared memory, 5a to 5C are reception control circuits, and 7a to 5C are reception control circuits.
7c is a data register, 8a to 8C are address registers, 10a to 10c are address buses, and lla to llc are data buses, which are the same as or equivalent to the conventional ones with the same reference numerals in FIG. Further explanation will be omitted.

9a-9C are arithmetic processing units corresponding to the arithmetic processing units 1a-IC shown in FIG. 8, and 12 is a scanning circuit corresponding to the scanning circuit 6 shown in FIG. Here, the arithmetic processing units 9a to 9c are different from the conventional arithmetic processing units 1 in that a priority is added to the shared memory request signal issued by each of the arithmetic processing units 9a to 9c.
It is different from a~IC. Furthermore, unlike the conventional scanning circuit 6, the scanning circuit 12 includes a timer 31 as a clock means for generating a clock signal, a delay circuit 32 as a delay means for delaying the clock signal from the timer 31 to generate a delayed clock, An OR circuit 33 serves as an OR means for ORing the clock signal from the timer 31 and the delayed clock from the delay circuit 32, and the output of this OR circuit 33 is sent from the control device of the arbiter device, which will be described later. It is comprised of an AND circuit 34 as a logical product means for logically multiplying the signal with the access permission control signal and outputting the result as a shared memory permission signal.

Reference numeral 13 stores the access range of the arithmetic processing units 9a to 9C currently accessing the shared memory 4, reads the arbitrarily designated shared memory access schedule range of the arithmetic processing units 9a to 9C, and stores the read access schedule. An address comparison circuit 14 compares the address of the range with the address of the access range stored at the time, and 14 reads the shared memory request signal with priority sent from the arithmetic processing units 9a to 9C, and The shared memory permission signal cyclically sent from the scanning circuit 12 is sent to the reception control circuits 5a to 5a associated with the corresponding arithmetic processing units 9a to 9C, taking into account the comparison results of the address comparison circuit 13 as necessary. This is a control device that controls allocation to the shared memory 5C and prevents the scanning circuit 12 from issuing the shared memory permission signal while the shared memory 4 is being accessed. Reference numeral 15 denotes an arbiter device comprising the address comparison circuit 13 and the control device 14.

Next, the operation will be explained. For example, assume that one arithmetic processing device 9a needs to write to the shared memory 4 during arithmetic processing. The arithmetic processing unit 9a has a shared memory 4
The priority is determined according to the urgency of the access, and the control device 14 in the admission control circuit 5a and the arbiter device 15,
A shared memory request signal with the priority added is issued, and the access range of the shared memory 4 is sent to the address register 8a via the address bus 10a, and write data is sent to the data register 7a via the data bus lla. The priority can be added by using the length of the shared memory request signal, the number of short signals issued within a certain period of time, or by providing a signal line for the priority irregularity.

Next, the admission control circuit 5a waits for a shared memory permission signal inputted from the scanning circuit 12 via the arbiter device 15,
The operation from the input of the shared memory permission signal to the completion of access to the shared memory 4 is the same as that described in the conventional example shown in FIG. It is the same as the thing.

On the other hand, the arbiter device 15 that has input the shared memory request signal
currently uses the shared memory 4 in any of the arithmetic processing units 9a to 9a.
The following operations are performed for two cases: when the processor 9C is accessing the shared memory 4, and when none of the arithmetic processing units 9a to 9C is accessing the shared memory 4.

First, a case will be described in which none of the arithmetic processing units 9a to 9C is accessing the shared memory 4 at the time when the shared memory request signal is input. Based on the priority added to the input shared memory request signal, the control device 14 in the arbiter device 15 sends the following information to all arithmetic processing devices 9a to 9C that are already waiting for a shared memory permission signal. Control is performed using a circular management table so that the shared memory permission signals sent from the scanning circuit 12 are given in order of priority.

Here, the scanning circuit 12 operates as follows.

The timer 31 generates a clock signal of a predetermined period, and this clock signal is divided into parts and the negative part is input to the delay circuit 32. This delay circuit 32 is a circuit in which when the input signal becomes "L", its output signal becomes "1" after a predetermined time T has elapsed.
3 and the other of the divided clock signals is logically summed. The output of this OR circuit 33 is input to an AND circuit 34 which is opened and closed by an access permission control signal sent from the control device 14 in the arbiter device 15. Therefore, only during the period when the access permission control signal is "1", a rectangular wave signal obtained by elongating the "!" state of the clock signal sent from the timer 31 is cyclically output as the shared memory permission signal. . FIG. 3 is a time chart showing the time relationship of each signal. Scanning circuit 1
2, the access permission control signal from the control device 14 is °'0
'', the generation of cyclic shared memory permission signals is stopped.

FIG. 4 shows the structure of the management table, which consists of a header and areas allocated to each of the processing units 9a to 9C. A pointer to a table assigned to the arithmetic processing units 9a to 9C to which the access permission signal is first given is stored in the header part, and which arithmetic processing unit 9a
If there is no request to access the memory 4 from ~9C, it is assumed that the pointer points to the header itself. In the area given to each arithmetic processing device 9a to 9C following the header, a pointer to the area allocated to the arithmetic processing device 9a to 9C to be granted access permission next is also stored. If there is no arithmetic processing unit 9a to 9C to which access permission should be granted next, the pointer points to the header.

Here, when the arithmetic processing device 9a inputs the shared memory request signal to the control device 14, the shared memory request signals from the arithmetic processing device 9b and the arithmetic processing device 9C have already been input to the control device 14, and each arithmetic processing device When the priorities added to the shared memory request signals 9a to 9c are arithmetic processing device 9b≧arithmetic processing device 9a>arithmetic processing device 9C, the state of the management table is as shown in FIG. 5(a). . That is, the pointer of the header points to the arithmetic processing unit 9b, and when the shared memory permission signal is input from the scanning circuit I2, the control device 14 transmits the shared memory permission signal to the arithmetic processing unit 9b.
Then, as shown in FIG. 5(b), a pointer to the area allocated to the arithmetic processing unit 9a to which shared memory access permission is granted next after the arithmetic processing unit 9b. The content of is stored in the header pointer, and then the management table is updated so that the arithmetic processing unit 9a is given access rights to the shared memory 4, and the access permission control number 13 to the scanning circuit 12 is set to 0''.
Issuance of the shared memory permission signal to the scanning circuit 12 is stopped.

When the arithmetic processing device 9b completes accessing the shared memory 4, the reception control circuit 5b sends an access completion signal to the arithmetic processing device 9b and the control device 14. In response, the control device 14 returns the access permission control signal to the scanning circuit 12 to "'I", thereby causing the scanning circuit 12 to resume issuing the cyclic shared memory permission signal.

In response to the shared memory permission signal whose issuance has been resumed in this way, the control device 14 then similarly sends out a shared memory permission signal to the reception control circuit 5a of the arithmetic processing unit 9a, and performs the same operation as described above. Repeatedly, the management table changes as shown in FIGS. 5(b) to 5(d).

Here, if the arithmetic processing unit 9b issues the shared memory request signal again with the highest priority in the state shown in FIG. 5(c), the state of the management table will be as shown in FIG. 6(b).
FIG. 6(a) is in the same state as FIG. 5(b). In this way, the control device 14
When a shared memory request signal from a to 9c is input, the management table is instantly updated based on the priority added to the shared memory request signal. Note that for items with the same priority, the input order is followed.

Next, the case where, for example, the arithmetic processing unit 9b is accessing the shared memory 4 at the time when the arbiter device 15 receives a shared memory request signal from the arithmetic processing unit 9a, for example, will be explained according to the flowchart shown in FIG. do.

The control device 14 in the arbiter device 15 compares the priority of the arithmetic processing device 9a to which the shared memory request signal has been input and the priority of the arithmetic processing device 9b currently accessing the shared memory 4 (step 5TI), here, the priority of the arithmetic processing unit 9b currently accessing the shared memory 4 is temporarily stored by the control device 14 at the time when the control device 14 sends the shared memory permission signal. . If the priority of the arithmetic processing device 9b currently accessing the shared memory 4 is higher or the same, the signal is added to the shared memory request signal issued by the arithmetic processing device 9a, as in the case described above. The content of the management table is updated with the assigned priority (step 5T2).

Further, as a result of the determination in step STI, if the priority of the arithmetic processing unit 9b currently accessing the shared memory 4 is lower, the control device 14 activates the address comparison circuit 13 to read the current shared memory I74. It is checked whether or not there is an overlap between the access range of the processing unit 9b currently accessing and the access range scheduled to be accessed by the processing unit 9a that has issued the shared memory request signal (step 5T).
3) If the result is 0 and even a partial overlap is recognized, the arithmetic processing unit 9a that issued the shared memory request signal continues accessing the shared memory 4 of the arithmetic processing unit 9b that is currently accessing it. is registered in the management table as in the case described above (step 572).

On the other hand, if no overlap is found in the access ranges, the control device 14 sends an interruption signal to the reception control circuit 5b of the arithmetic processing device 9b currently accessing the shared memory 4. Upon receiving the interruption signal, the reception control circuit 5b temporarily saves and shares the access state of the shared memory 4 up to that moment so that the current operation can be continued when permission to access the shared memory 4 is received later. Access to the memory 4 is interrupted (step 5T4).

When access to the shared memory 4 by the processing unit 9b is interrupted in this way, the control unit 14 puts the processing unit 9a that issued the shared memory request signal in a state where it can access the shared memory 4 with the highest priority. , the contents of the management table are updated so that the arithmetic processing unit 9b, which had been accessing the shared memory 4 up until then, can access the shared memory 4 second (step 5T5).

After the access to the shared memory 4 is completed, the arithmetic processing unit Z9
When the access end signal is sent from a, the control device 1
4 sets the access permission control signal to the scanning circuit 12 to "'1"
Then, the scanning circuit 12 is caused to resume cyclic operation (step 5T6), and a shared memory permission signal from the scanning circuit 12 is waited for.

When the shared memory permission signal is input again, the control device 14 sends the shared memory permission signal to the reception control circuit 5b of the arithmetic processing unit 9b having the highest priority registered in the management table, and interrupts the process. The access to the shared memory 4 is restarted.

As described above, even when the shared memory 4 is being accessed, the high-priority arithmetic processing units 9a--
It becomes possible to give access rights to the shared memory 4 preferentially to 9C.

In the above embodiment, the address comparison circuit 13 determines which data is used by the arithmetic processing unit 9a to 9cm currently being accessed.
The access range of the shared memory 4 currently being executed is compared with the scheduled access range of the shared memory 4 by the arithmetic processing units 9a to 9C that issued the shared memory request signal with a higher priority. Although we have shown the method that determines whether or not to interrupt access to the shared memory 4 of
Priority is given to the arithmetic processing by the arithmetic processing units 98 to 9c that are currently accessing, and only the arithmetic processing units 9a to 9C that are waiting to access the shared memory 4 are granted access rights to the shared memory 4 according to the above-mentioned priority. Allocation control may also be performed. In that case, the address comparison circuit 13 is not required in the arbiter device 15.

〔Effect of the invention〕

As described above, according to the present invention, priority is added to the shared memory request signal issued by the arithmetic processing unit, a simple arbiter device is provided, and the scanning circuit is arranged in an OR mode of clock means and delay means. Since the shared memory permission signal is given to the reception control circuit of the arithmetic processing unit that issued the shared memory request signal with the highest priority at that time, the configuration of the conventional multiprocessor system is significantly changed. Not only is it possible for each arithmetic processing unit to easily access the shared memory preferentially as necessary, but also the cyclic shared memory permission signal generation operation does not stop unnecessarily. Therefore, it is possible to access the shared memory efficiently, improving the throughput of the entire system, and achieving high reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of its scanning circuit, FIG. 3 is a time chart for explaining its operation, and FIG. FIG. 5 is an explanatory diagram showing the configuration of the management table of this embodiment, FIGS. 5 and 6 are explanatory diagrams showing the operational status of the management table, and FIG. 7 is a flowchart showing the operation of the control device of this embodiment. FIG. 8 is a block diagram showing a conventional multi-processor system, FIG. 9 is a block diagram showing an example of the configuration of its scanning circuit, and FIG. 10 is a time chart for explaining its operation. 4 is a shared memory, 5a to 5C are reception control circuits, 9a to 9
c is an arithmetic processing unit, 12 is a scanning circuit, 14 is a control device,
15 is an arbiter device, 3I is a clock means (timer),
32 is a delay means (delay circuit), 33 is an OR means (
34 is a logical product means (AND circuit). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation (2 others) ■ 50~5c'e protection control time τ care a ~7c', 7=9shi:ノZ9 8o~8c: completed Shimata Regis 9

Claims (1)

[Claims] A shared memory is commonly used by a plurality of arithmetic processing units that execute various arithmetic processing operations, and a scanning circuit that generates a shared memory permission signal for controlling access to the shared memory by the arithmetic processing units; The shared memory request signal issued by the corresponding arithmetic processing device and the shared memory permission signal generated by the scanning circuit are input to the corresponding arithmetic processing device. and an admission control circuit that grants access rights to a memory, in which the shared memory request signal corresponds to the arithmetic processing unit that issued the shared memory request signal, according to the priority added to the shared memory request signal. The admission control circuit is provided with an arbiter device including a control device that provides the shared memory permission signal generated by the scanning circuit, and the scanning circuit is connected to a clock means for generating a clock signal and a delay clock for delaying the clock signal. a delay means for generating the clock signal, an OR means for ORing the clock signal and the delayed clock, and a logical product of the output of the OR means and the access permission control signal sent from the control device; 1. A multiprocessor system comprising: AND means for outputting a shared memory permission signal.