JPH064314A - Inter-task synchronizing communication equipment - Google Patents

Abstract

PURPOSE:To provide an inter-task synchronizing communication equipment provided with a means for decreasing information in a queue buffer. CONSTITUTION:The number of communication data stored in a queue buffer 1 is stored in a counter 2 and based on the value of the counter 2, a priority control part 3 refers to a priority managing table 4 registering the priority of producer/consumer tasks 6 and 7 to be transmitted/received through the queue buffer 1. By the control of the priority control part 3, the execution tasks of the producer/consumer tasks 6 and 7 are switched by a dispatcher 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a word processor and a database or a task-to-task synchronous communication device of a control device such as a robot. The present invention relates to an intertask synchronous communication device that requires processing.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional inter-task synchronous communication device is a controller 10 of a hard disk 106.
After 5 receives the read and write commands,
A delay time is required until the transfer of data to be accessed via the read / write device is required, and the CPU
Reference numeral 103 is used for a task for preparing data processing and write data executed during the waiting time of the controller 105, and for synchronous communication between tasks for controlling the controller 105.

The address and data bus 108 is a CPU
103 is the main storage device 101 or the hard disk 10
6 is used for data transfer between the CPU 103 and the specified target.

The controller 105 is used to convert a command issued by the CPU 103 into an electric signal determined for each device, and conversely to convert the device status information into data that can be understood by the CPU 103.
6 is provided with a buffer for holding data transferred to and from.

The CPU 103 performs data transfer between the main storage device 101 or the internal register and this buffer, processing of read data or preparation of write data.

First, in the first procedure, the CPU 103 copies the address of the input data into the buffer and notifies the controller 105 of that fact, and the controller 105 sets a flag when the input operation is completed.

The CPU 103 continues to test this flag until it succeeds, and if the test is successful, the CPU 103 takes out the read data from the buffer, processes the read data, and outputs the data in the same procedure. Be seen.

As described above, if the data processing process and the control process of the controller 105 are sequentially performed, the CPU 103 consumes only the process of a flag test as to whether the controller 105 is still in operation.

In the second procedure, the CPU 103 copies the address of the input data into the buffer, and the controller 1
This is notified to 05, and the processing of the data that has been input in advance is executed.

When the input operation is completed, the controller 105 generates an interrupt to the CPU 103 and the CPU 10
3 retrieves the read data from the buffer, issues the next command to the controller 105, and returns control to the interrupted process.

If the interrupt is delayed by prioritizing a consumer task such as data processing, the process is executed at the timing shown in FIG. 7A, and even if the input data is accumulated in the queue buffer, the queue is queued. Until the buffer is empty
The read data is processed, resulting in a long processing time.

On the contrary, when the producer task such as the control process of the controller 105 is prioritized to immediately respond to the interrupt, the process is executed at the timing shown in FIG. 7B.

However, since there is a limit to the amount of data that can be stored in the queue buffer, when the queue buffer is full, the operation of writing data to the queue buffer is delayed until there is space in the queue buffer, and the output is output. The same procedure occurs and the same phenomenon occurs.

[0014]

Since such a conventional inter-task synchronous communication device does not have a means for reducing the information in the queue buffer, when the queue buffer becomes full, the producer task And task switching of consumer tasks occurs frequently and causes overhead.

Further, when the producer task finishes producing all the data, the consumer task does not have the CPU 103 for the first time.
In order to monopolize the data and accelerate the processing, when the intermediate stage of data production is seen, the data is in the queue buffer, and the data is stagnated in an unprocessed state.

Further, when the consumer task uses the VRAM and shares it with the graphics accelerator, the producer task is always prioritized, so that the consumer task has the execution right while acquiring the VRAM and the graphics accelerator. And the wait time of devices such as graphics accelerators increases.

[0017]

In order to solve the above problems, an intertask synchronous communication apparatus of the present invention holds a queue buffer for storing communication data and the number of communication data stored in this queue buffer. And a priority control unit that changes the execution priority of each task that transmits / receives the communication data based on the counter value.

Further, the inter-task synchronous communication device of the present invention is
A multiprocessor, a shared queue buffer that stores transmission data, a counter that holds the number of communication data stored in this queue buffer, and communication data between the processors of the multiprocessor under the command of this multiprocessor And a priority control unit for changing the execution priority of each task for transmitting / receiving the data based on the counter value.

Further, in the inter-task synchronous communication device of the present invention, when the priority of the transmission task is increased, the execution priority of each task of the priority control unit is changed when the transmission task transmits or the reception task receives. It is characterized by doing.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an inter-task synchronous communication device according to an embodiment of the present invention.

FIG. 2 is a flow chart of the producer task targeted by the intertask synchronous communication apparatus according to one embodiment of the present invention.

FIG. 3 is a flowchart of consumer tasks targeted by the intertask synchronization communication device according to one embodiment of the present invention.

FIG. 4 is a flow chart of the priority control unit of the inter-task synchronous communication apparatus according to one embodiment of the present invention.

FIG. 5 is a time chart showing an execution state of the inter-task synchronous communication device according to the embodiment of the present invention.

An intertask synchronous communication apparatus according to an embodiment of the present invention has a configuration as shown in FIG.
However, for example, it is accessed only by a system call under the control of the OS, and a plurality of communication data are stored in a partial area in the main memory.

The counter 2 is a partial area in the main memory whose access is controlled by using, for example, a semaphore method, holds the number of communication data stored in the queue buffer 1, and the queue buffer is empty and full. At that time, the dispatcher 5 is deprived of the execution right of each of the consumer task 7 attempting to receive and the producer task 6 attempting to send.

The priority control unit 3 is, for example, a CPU
Counter 2 which is a part of the OS program executed by
Based on the value of, the priority of the producer task 6 and the consumer task 7 registered in the priority management table 4 for transmitting / receiving data via the queue buffer 1 is changed.

The priority management table 4 is, for example, a hash table stored in the main storage device, and stores tasks in an executable state for each priority.

Dispatcher 5 for switching tasks
Refers to the priority management table 4 and switches the execution tasks such as the producer task 6 and the consumer task 7 according to the priority scheduling method, for example.

The producer task 6 is a task for performing the processing shown in FIG. 2, for example.
Data is transmitted via the queue buffer 1.

The consumer task 7 is a task for performing the processing shown in FIG. 3, for example, and receives the data transmitted by the producer task 6 via the queue buffer 1.

Next, the operation of the inter-task synchronous communication apparatus according to the embodiment of the present invention will be described with reference to FIGS.

First, in the initial state, the producer task 6 has the priority, and the producer task 6 performs the processing shown in FIG. 2 and notifies the controller for controlling a device such as a hard disk of the address to be read and waits. Enter the state.

After that, the process returns from the waiting state, the data is read in the process 21 and the process proceeds to the next step. In the process 22, it is checked whether the reading is completed. If it is completed, the process is completed. Process 2 if you can
Go to 3.

The queue buffer 1 in the initial state is empty,
In process 23, the data is stored in the queue buffer 1 without being deprived of the execution right, the value "1" is held in the counter 2, and the process proceeds to the next step.

In the process 24, the address to be read next is notified to the controller and the controller waits until an interrupt from the controller arrives. The dispatcher 5 searches the priority management table 4 and executes the task with the highest priority. And the consumer task 7 obtains the execution right to perform the processing shown in FIG.

In process 31, data is taken out from the queue buffer 1.

Here, assuming that the communication data amount is very large, "retrieving" data from the queue buffer 1 is actually equivalent to obtaining the right to read the data in the queue buffer 1. It is assumed that the value of the counter 2 does not change until the process 32 is completed and the right to read the data in the queue buffer 1 is relinquished even if the data is taken out.

Since the producer task stored the data in the process 23 in the previous step, since it is not empty, the process proceeds to the next step without being robbed of the execution right. In the process 32, for example, the fetched image data is drawn in the VRAM. Is processed.

In the middle of this process, the controller notifies by interrupt that the data reading from the hard disk has been completed, and the control is transferred to the dispatcher 5.

Therefore, the dispatcher 5 searches the priority management table 4, and the producer task 6 which has been made executable by the interrupt of the controller has a higher priority than the consumer task 7 which has been executed so far. Therefore, the execution task is switched and control is transferred to the producer task 6.

The processing is performed in the same manner as described above, the counter 2 holds the value "2", the producer task 6 similarly shifts to the waiting state, and the control is returned to the consumer task 7.

When the process 32 is completed, the counter 2 holds the value "1", the process 33 determines the end of the drawing process, and if not completed, the process returns to the process 31.

In this way, in the process of transition of the execution task, constants A and B having a relation of 0 ≤ A ≤ B ≤ queue buffer size, for example, are set in advance, and the priority control unit 3 is set in FIG. As shown, the queue buffer 1 is called at the timing of transmission / reception with respect to the queue buffer 1, and the number of communication data in the queue buffer is checked in process 41.

Based on the check result, the process is terminated, or the process 42 or the process 43 is performed, and the communication data is gradually accumulated from the empty state of the queue buffer 1 to the value "A" of the counter 2 at the initial stage. .

When the counter 2 reaches the value "A", the consumer task 7 tries to lower the priority relative to the producer task 6, but the consumer task 7 is already compared with the producer task 6. Nothing is processed because the priority of is low.

After that, when the value of the counter 2 becomes "B", the producer task 6 as a whole is compared with the consumer task 7.
To lower the priority of the consumer task 7 to make the consumer task 7 a priority task.

When the consumer task 7 becomes the priority task, the dispatcher 5 continues to give the execution right to the consumer task 7 even when the interrupt from the controller occurs.
As shown in FIG. 5, the consumer task 7 is continuously executed, the value of the counter 2 continues to decrease, and when the value of the counter 2 becomes “A”, the producer task 6 is generally treated. The priority of the consumer task 7 is lowered to make the producer task 6 a priority task.

Thereafter, the same processing is repeated. Next, a conventional inter-task synchronous communication device will be described with reference to the drawings.

FIG. 6 shows a configuration example of a conventional inter-task synchronous communication device.

FIG. 7 is a time chart (A) when the consumer task is always the priority task and a time chart (B) when the producer task is always the priority task in the conventional inter-task synchronous communication device. is there.

As shown in FIG. 6, a conventional inter-task synchronous communication device is a controller 105 of a hard disk 106.
Requires a delay time from the reception of the read / write command to the start of the transfer of the data to be accessed via the read / write device.
Reference numeral 03 is used for the task of preparing data processing and write data executed during the waiting time of the controller 105 and the synchronous communication between the tasks of controlling the controller 105.

The address and data bus 108 is a CPU
103 is the main storage device 101 or the hard disk 10
6 is used for data transfer between the CPU 103 and the specified target.

The controller 105 is used to convert a command issued by the CPU 103 into an electric signal determined for each device, and conversely to convert the device status information into data that can be understood by the CPU 103.
6 is provided with a buffer for holding data transferred to and from.

The CPU 103 performs data transfer between the main storage device 101 or internal register and this buffer, processing of read data or preparation of write data.

First, in the first procedure, the CPU 103 copies the address of the input data into the buffer and notifies the controller 105 of that fact, and the controller 105 sets a flag when the input operation is completed.

The CPU 103 continues to test this flag until it succeeds, and if the test succeeds, the CPU 103 takes out the read data from the buffer, processes the read data, and outputs the data in the same procedure. Be seen.

As described above, when the data processing process and the control process of the controller 105 are sequentially performed, the CPU 103 is consumed only for the flag test of whether the controller 105 is still in operation.

In the second procedure, the CPU 103 copies the address of the input data into the buffer, and the controller 1
This is notified to 05, and the processing of the data that has been input in advance is executed.

When the input operation is completed, the controller 105 generates an interrupt to the CPU 103, and the CPU 10
3 retrieves the read data from the buffer, issues the next command to the controller 105, and returns control to the interrupted process.

If the consumer task such as data processing is prioritized and the interrupt is delayed, the process is executed at the timing shown in FIG. 7A, and the queue buffer is processed even if the input data is accumulated in the queue buffer. The read data is processed until it becomes empty.
It takes a long processing time.

On the contrary, when the producer task such as the control processing of the controller 105 is prioritized and the interrupt is immediately responded to,
The process is executed at the timing shown in FIG.

However, since the amount of data that can be stored in the queue buffer is limited, when the queue buffer is full, the operation of writing data to the queue buffer is delayed until there is space in the queue buffer, and the output The same procedure occurs and the same phenomenon occurs.

[0065]

As described above, according to the inter-task synchronous communication device of the present invention, the priority of the communication task is controlled by the priority control section based on the number of communication data stored in the queue buffer. It has the effect of speeding up the processing of communication data.

Further, since there is no task switching when the queue buffer is full, the number of task switching is reduced, and the processing of the entire system is speeded up.

Furthermore, when each task shares the VRAM with the drawing accelerator, the RUN state that occupies the device is reduced, so that the device can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram of an inter-task synchronous communication device according to an embodiment of the present invention.

FIG. 2 is a flowchart of a producer task targeted by the inter-task synchronization communication device according to the embodiment of the present invention.

FIG. 3 is a flowchart of consumer tasks targeted by the inter-task synchronization communication device according to the embodiment of the present invention.

FIG. 4 is a flowchart of a priority control unit of the inter-task synchronous communication device according to the embodiment of the present invention.

FIG. 5 is a time chart showing an execution state of the inter-task synchronous communication device according to the embodiment of the present invention.

FIG. 6 is a configuration example of a conventional inter-task synchronous communication device.

FIG. 7 is a time chart (A) when a consumer task is always a priority task and a time chart (B) when a producer task is always a priority task in a conventional inter-task synchronization communication device.

[Explanation of symbols]

1 Queue Buffer 2 Counter 3 Priority Control Unit 4 Priority Control Unit (Priority Management Table) 5 Priority Control Unit (Dispatcher) 6 Queue Buffer (Producer Task) 7 Queue Buffer (Consumer Task)

Claims (4)

[Claims] 1. A queue buffer for storing communication data, a counter for holding the number of communication data stored in the queue buffer, and an execution priority of each task for transmitting / receiving the communication data as counter values. An inter-task synchronous communication device comprising: a priority control unit that changes based on the above. 2. A multiprocessor, a shared queue buffer for storing transmission data under a command of the multiprocessor, a counter for holding the number of communication data stored in the queue buffer, and each of the multiprocessors. An inter-task synchronous communication device, comprising: a priority control unit that changes the execution priority of each task that transmits / receives communication data between processors based on a counter value. 3. When the priority of the transmission task is increased, the execution priority of each task of the priority control unit is changed when the transmission task transmits or the reception task receives. The inter-task synchronization communication device described. 4. When increasing the priority of the transmission task, the execution priority of each task of the priority control unit is changed when the transmission task transmits or the reception task receives. The inter-task synchronization communication device described.