JPH0773136A - Operation method for computer system - Google Patents

Abstract

PURPOSE:To reduce the time lag of a circuit operation to improve efficiency by read/write-controlling a device by a means of a DMA cycle when CPU accesses to the device through the use of a DMA signal bus. CONSTITUTION:When CPU 4 accesses to I/O devices 9 and 10 or a memory 11, the devices 9, 10 and 11 are read/write-controlled by the DMA cycle, and data is inputted/outputted. It is assumed that CPU 4 accesses to the I/O devices 9 and 10 or the memory 11 while a DMA controller 6 transfers DMA data. In such a case, DMA controller 6 can evacuate a DMA bus 2 to CPU with the DMA cycle as a unit. Thus, CPU 4 can access to the target devices 9, 10 and 11 in the period of the DMA cycle, and therefore time when CPU 4 occupies the DMA bus 2 can be set to a minimum. Thus, a processing can efficiently be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of operating a computer system having a signal bus for a CPU to access a specific device and a signal bus for a DMA controller to access another device.

[0002]

2. Description of the Related Art The basic computer system is CP
A U, a memory, an I / O device, a DMA controller, and the like are connected to one signal bus and configured. The signal bus is composed of an address bus and a data bus.

In this case, the CPU outputs an address signal from the address bus to specify a memory address or an I / O address to be accessed. Then, data is input / output to / from the specified memory or I / O device via the data bus. When the CPU activates the DMA controller, the DMA controller uses the signal bus to execute the data input / output operation for each device, as in the case of the CPU.

In the case of the above configuration, the DMA controller is
During operation, the CPU occupies the signal bus, and therefore the CPU cannot access each device by using the signal bus at the same time.

As a method for eliminating such inconvenience, for example, there is a proposal found in Japanese Patent Laid-Open No. 3-286241. This proposal proposes a signal bus for the CPU used when the CPU accesses a specific device, and a DMA used when the DMA controller accesses another device.
And a signal bus for use. According to this proposal, the access operation of the CPU and the access operation of the DMA controller can be simultaneously executed, so that the computer system can efficiently execute various processes in a short time.

On the other hand, in the case of the above configuration, the CPU needs to access each device on the DMA signal bus side as necessary. In the above proposal, the CPU signal bus and the DMA signal bus are connected when performing such an access operation.

[0007]

Here, as shown in FIG. 12, it is assumed that an access request is issued from the CPU to a device on the signal bus line for DMA during the execution of DMA data transfer by the DMA controller. The DMA data transfer operation is executed in units of a prescribed cycle T1 called a DMA cycle. Therefore, in this case, when one cycle being executed is completed, the DMA data transfer operation is suspended. Then, the CPU executes predetermined data transfer in units of another prescribed cycle T2 called a CPU cycle. After that, the DMA data transfer operation is restarted in the DMA cycle.

However, since the DMA cycle and the CPU cycle operate independently of each other, the CPU must follow the procedure of monitoring the DMA cycle, detecting the end of the DMA cycle, and then giving up the bus. . Further, when the bus is connected, the CPU accesses each device on the DMA signal bus side, and when the access is completed, it is necessary to disconnect the bus and hand over the bus to the DMA controller side. There has been a problem that a computer system cannot operate efficiently because a time lag of time T3 and T4 for the procedure occurs.

Further, if the DMA signal bus access by the CPU is by a string instruction, the original DMA transfer is stopped until the continuous access by the string instruction is completed, and it is necessary to provide service at regular intervals. If there is a certain DMA transfer request, it cannot be handled.

The string instruction will be described below. Computer systems often handle data defined continuously in memory. For example, there is so-called block transfer in which 100 Hbytes of data starting from address 8000H of memory are transferred to an area up to address 90FFH starting from address 9000H of memory. In addition, there is a comparison operation for comparing the value of a register in the CPU with the data continuously defined in the memory. A string instruction performs these operations at once on data defined continuously in memory.

Here, a problem when the CPU continuously accesses the device on the DMA bus by a string instruction or the like will be described with reference to FIG.

In FIG. 1, DMAs 1 to 5 are equal DMA requests without priorities from devices on the DMA signal bus side (DMA request sources). Where DMA1
Is a DM that should be appropriately processed (serviced) at regular intervals
A request.

When the DMA controller sequentially services the request sources of DMA1 to DMA5 in the order requested, DMA3, DMA1 and DMA2.
Since the CPU has made an access request to the DMA bus during the second service, when the DMA2 service ends, the access request is accepted. However, since the CPU access is continuous access by the string instruction, DM
The A bus is exclusively used for continuous access executed in the CPU cycle, and requests from the request sources of the DMA1 to DMA5 are kept waiting until the continuous access ends.

In particular, it becomes impossible to service the DMA 1 which should be serviced at regular intervals within a fixed period.

An object of the present invention is to solve the above problems and provide an efficient method for operating a computer system.

[0016]

To this end, the present invention provides C
When the PU accesses the device on the side of the signal bus for DMA, the specified period of the DMA controller, that is, DMA
In a cycle, read / write control is performed on the device to input / output data.

Further, the DMA request is given a priority, the priority is divided into fixed priority and rotation priority, the presence or absence of the request is monitored while being sampled, and if the request is latched, the services are serviced in order according to the priority. If the service is for the rotation priority request, the rotation priority priority is rotated after the service ends, while the latched request is cleared and re-sampled at regular intervals.

When a signal bus access request for DMA of the CPU is made independent of other DMA requests, and when there is an access request of the CPU, the access of the CPU is prioritized to be serviced, and there is no access request of the CPU. Attempts to service other DMA requests in priority order.

[0019]

When the device access of the DMA controller is temporarily suspended and the device access of the CPU is executed, it is sufficient to temporarily suspend the device access in units of DMA cycle, which reduces the time lag of the circuit operation and also the DMA. The computer system can operate efficiently because it can appropriately respond to the DMA request of the device on the bus side.

[0020]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention.

In this figure, this computer system is provided with two sets of signal buses, a CPU bus 1 and a DMA bus 2. The CPU bus 1 is the address bus 1a
And a data bus 1b, and the DMA bus 2 is composed of an address bus 2a and a data bus 2b.

The bus buffer circuit 3a connects the address bus 1a and the address bus 2a as needed. The bus buffer circuit 3b and the buffer & latch circuit 3c connect the data bus 1b and the data bus 2b. It is a thing. When the buses are connected by the bus buffer circuits 3a and 3b, the signal on the CPU bus 1 side is the DMA bus 2
When the buffer & latch circuit 3c connects the buses, the signal of the data bus 2b is output to the data bus 1b.

The CPU bus 1 includes a CPU 4, a DMA bus request circuit 5, a DMA controller 6, a memory 7 and an I.
/ O device 8 is connected. On the DMA bus 2,
In addition to the above DMA controller 6, an I / O device 9,
10 and the memory 11 are connected. The competition control circuit 12 is arranged to receive signals from the DMA bus request circuit 5 and the I / O devices 9 and 10 and output signals to the respective parts.

The memory 7 stores a control program for the CPU 4 and other data. This memory 7 and I
The / O device 8 is accessed only by the CPU 4. The I / O devices 9, 10 and the memory 11 are D
In addition to being accessed by the MA controller 6, the CPU 4 is also accessed as necessary.

The CPU 4 monitors and controls the entire system. The DMA bus request circuit 5 issues a predetermined request to the contention control circuit 12 in order to use the DMA bus 2 when the CPU 4 accesses the I / O devices 9, 10 or the memory 11. Contention control circuit 12
Arbitrates requests from the DMA bus request circuit 5 and the I / O devices 9 and 10, and connects or disconnects the CPU bus 1 and the DMA bus 2 as needed.

The DMA controller 6 executes data transfer between the I / O devices 9, 10 and the memory 11 without the intervention of the CPU 4.

With the above configuration, FIG. 2 shows an example of an operation procedure when the computer system of this embodiment executes one process.

That is, when the operation of this computer system is started, the CPU bus 1 and the DMA bus 2 are electrically separated (process 101). In this state, CPU4
Reads the control program from the memory 7 and starts the operation. Then, as shown in FIG.
Accesses the memory 7 and the I / O device 8 via the CPU bus 1 and transfers data to and from them (process 102).

Here, for example, I / O devices 9 and 10
Suppose you need to transfer data to and from memory. In this case, the CPU 4 activates the DMA controller 6 (process 103). As a result, the DMA controller 6 executes data transfer between the I / O devices 9, 10 and the memory 11 via the DMA bus 2 as shown in FIG. This DMA data transfer is executed in parallel with the data transfer of the CPU bus 1 (process 104).

Next, it is assumed that the CPU 4 needs to output data to the I / O device 9 or 10 or write data to the memory 11. In this case, the CPU 4
A request for data output to the DMA bus 2 side is issued to the DMA bus request circuit 5 (process 105). Then, the address of the I / O device 9, 10 or the address of the memory 11 is output from the address bus 1a, and
6), output data from the data bus 1b (Process 10)
7).

By the way, the CPU 4 accesses each device in a prescribed CPU cycle, and the DMA controller 6
Accesses each device in another DMA cycle.
In this case, the CPU cycle and the DMA cycle are asynchronous. Therefore, the CPU 4 here waits for the end of one DMA cycle in operation (process 108).

Then, only the device control function of the DMA controller 6 is enabled. That is, when accessing each device, the DMA controller 6 outputs each address of the transfer source and the transfer destination, controls the read / write of the target device, counts the number of transfer data, and completes the transfer of a predetermined amount of data. Then, the CPU 4 is interrupted.
Here, of those functions, only the write control function for the device is enabled and the other functions are disabled (1
09).

Next, the CPU bus 1 and the DMA bus 2 are connected by the bus buffer circuits 3a and 3b. As a result, the signal of the address bus 1a is transferred to the address bus 2a side,
The signal of the data bus 1b is output to the data bus 2b (process 110). Then, the DMA controller 6
Performs write control of the target device in a predetermined DMA cycle (process 111).

As a result, as shown in FIG. 3C, C
The data output from the PU 4 is the I / O device 9, 1
0 or output to the memory 11. This output operation is executed in one DMA cycle. When this one cycle ends, the CPU bus 1 and the DMA bus 2 are separated (process 112). As a result, the state of the processing 104 is returned to.

Next, in the state of the above processing 104, C
It is assumed that the PU 4 needs to input data from the I / O device 9 or 10 or read data from the memory 11. In this case, as shown in FIG.
U4 issues a request to the DMA bus request circuit 5 to input data via the DMA bus 2 (process 113).

Then, as described above, the address bus 1a
The address of the access destination is output to (step 114). After this, wait for the end of the operating DMA cycle (Process 11
5). Then, in this case, only the read control function for the device of the DMA controller 6 is enabled (Processing 11
6)

Next, the CPU bus 1 and the DMA bus 2 are connected. However, in this case, the bus buffer circuit 3a outputs a signal from the address bus 1a to the address bus 2a, while the buffer & latch circuit 3c outputs a signal from the data bus 2b to the data bus 1b (process 11).
7).

Next, the DMA controller 6 performs read control of the target device (process 118). As a result, as shown in FIG. 3D, the I / O devices 9, 10
Alternatively, the data is read from the memory 11.

At the end of the DMA cycle, the buffer & latch circuit 3c latches the read data (process 119). Then, the CPU bus 1 and the DMA bus 2 are separated (process 120). After this, the CPU 4
The data latched in the buffer & latch circuit 3c is read (process 121).

In this way, the state of the processing 104 is returned to. After that, the CPU 4 and the DMA controller 6
Each operation will be executed independently.

FIG. 5 is a time chart showing an example of the above operation. That is, assuming that the specified cycle, which is the DMA cycle, is T1, the DMA bus 2 is shown in FIG.
As shown in, the address signal and the data signal are transferred at the timing synchronized with the DMA cycle.

On the other hand, the specified cycle which is a CPU cycle is T
If the number is 2, the CPU bus 1 transfers the address signal and the data signal at the timing synchronized with the CPU cycle, as shown in FIG.

Here, it is assumed that a data output request from the CPU 4 to the DMA bus 2 is issued as shown in FIG. 3C during the execution of one DMA cycle operation. This is the operation described in the process 105. In this case, the CPU bus 1 and the DMA bus 2 are immediately connected in the next DMA cycle as shown in FIG. This is the operation of process 110. And from CPU4 to D
Data will be output to any device on the MA bus 2 side.

Also, when the data input request from the DMA bus 2 side described in the processing 113 is issued, the CPU bus 1 and the DMA bus 2 are immediately connected. This is the operation of process 117. Then, the data is read from any device on the DMA bus 2 side. In this case, as shown in (e) of the figure, the read data is latched in the buffer & latch circuit 3c at the end of the DMA cycle, and even after that, the CPU 4 can input the read data. .

As described above, in this embodiment, the CPU 4
However, when accessing the I / O devices 9, 10 or the memory 11, the devices are read / write-controlled in a DMA cycle to input / output data.

Therefore, DM by the DMA controller 6
When the CPU 4 accesses a device on the side of the DMA bus 2 during execution of the A data transfer, the DMA controller 6
Need only yield the DMA bus 2 to the CPU 4 in units of DMA cycles. As a result, the access operation of the target device by the CPU 4 is executed during the DMA cycle, so that the time when the DMA bus 2 is occupied by the CPU 4 can be minimized.

As a result, the time lag of circuit operation is reduced, and the computer system can operate efficiently.

Further, in the present embodiment, when the CPU 4 accesses each of the above devices, some functions of the DMA controller 6 are disabled and the read / write control of those devices is executed by the DMA controller 6. Therefore, it is not necessary to provide a dedicated circuit for executing such read / write control.

According to the method described above, the CPU
The MA bus can be accessed in the DMA cycle. Next, an embodiment of a method for enabling the DMA signal bus access from the CPU without stopping the DMA transfer of the device on the DMA signal bus side will be described in detail. Explained.

First, the configuration of the competition control circuit 12 will be described with reference to FIG.

In the figure, latch circuits 41 and 42 latch high priority requests and low priority requests by the same sampling clock. Note that the sampling request is not latched during the service period for the latched request.

The requests latched by the latch circuit 41 are arbitrated by the fixed priority circuit 43 in a fixed priority order, and the latch circuit 4
The requests latched by 2 are arbitrated by the rotation priority circuit 44 in the priority order of rotation.

Then, the service right circulation circuit 45 generates various signals for servicing the latched requests in order of priority. Further, the slice timer circuit 46 counts down from the set value set by the CPU, and outputs a reset signal to the latch circuits 41 and 42 when it reaches 0 (timeout). After outputting the reset signal, the countdown operation is repeated again from the set value.

The latch circuits 41 and 42 reset the request latched by this reset signal, sample and latch the request again, and repeat the above operation. If the slice timer times out during service for any request, the request is reset after the service ends.

The operation of the present embodiment configured as described above will be described with reference to the timing charts of FIG. 7 and FIG. 8 showing transition states of service right.

FIG. 7 shows in what priority the latched request is serviced. (*) Means a service right, and changes according to the overall priority order determined by the priority order state of rotation priority. The service right (*) is not passed to the request that is not latched. Also, every time the slice timer times out, the service right (*) is forcibly transferred to the initial state DMA1. Also, if you latch the request,
The service right (*) is forcibly transferred to the initial state DMA1. However, even if the service right shifts to the initial state, the priority order of rotation priority retains that state. The rotation priority status changes when the rotation priority request is serviced.

In FIG. 8, DMA1 and DMA2 are high priority request sources, and DMA3 to DMA6 are low priority request sources. Then, an access request from the CPU is assigned as DMA1. Although the sampling of the request status is always performed when the latched request is not in service, S1 to S8 shown in FIG. 8 are at least one of the service request status samplings. It shows the case where is latched.

First, the DM is always sampled.
Since only the A4 request is active, this request is sampled and latched (S1). Then, the service for the DMA4 is performed. Since the DMA4 is assigned as a low-priority request source, when the service ends, the priority of the rotation priority unit shown in FIG. 7 is the DMA5 next to the currently serviced DMA4, which is the highest priority. The state becomes (202). When the low priority request source is not serviced, the priority order of the rotation priority unit does not change.

Next, when the service of the DMA4 is completed, the request state is sampled and latched (S
2). At this time, since the request of DMA2 is active, DMA2 is serviced next. Also, DMA
Since the in-service slice timer of No. 2 times out, the request state latched after the end of the DMA2 service is reset (in this case, the latched request is DMA
Since it was only 2, there is no request to be reset. ), And the request state is sampled and latched again (S3). The status of the priority order after the service of the DMA2 remains (202) because the DMA2 is not the rotation priority request source.

At this time, since the requests of DMA3 and DMA5 are active, DMA5 and DMA3 are serviced in this order according to the priority state (202). The priority status after this service is (203) after the service of DMA5 and (20) after the service of DMA3.
It becomes 1).

When the service of the DMA3 is completed, the request state is sampled and latched again (S
4). At this time, since only the request of DMA1 (CPU) is active, the DMA1 (CPU) is serviced. After the service of DMA1 is completed, sampling is performed again and the requests of DMA2 and DMA6 are latched (S5). First, the DMA2 having the highest priority is serviced. During this service, since the slice timer times out, the DMA6 request currently latched is reset after the DMA2 service ends, and the request including the DMA6 request is sampled and latched again (S
6). At this time, the requests of DMA1 and DMA6 are latched, and DMA1 and DMA6 are serviced in descending order of priority. After the service of the DMA 6 is completed, the priority order state is (200).

After the service of DMA6 is completed, the request is sampled again, and at this time, the requests of DMA1 and DMA4 are latched (S7). The services here are also in order of priority D
MA1 and DMA4 are serviced in this order. After the service is completed, the state of the rotation priority section becomes (202).

Since the slice timer times out immediately after the end of the DMA4 service, the latched request is reset (here, there is no latched request), the request is sampled again, and the DMA1 and DMA2 requests are latched. (S8). And DM according to priority
Services are provided in the order of A1 and DMA2.

As described above, the request sources are divided into the fixed priority and the rotation priority, the request states of all the request sources are latched by one sampling, and the service having the highest priority is serviced and the slice is sliced. Since the timer resamples at regular intervals, fixed priority requests can always be serviced at regular intervals.

Further, even if the total time for servicing the requests latched in one sampling is longer than the set time of the slice timer, it is possible to service the requests with low priority on average.

That is, DMA1 to DMA6 in the case of FIG.
Depending on the setting of the slice timer, if all request sources request service frequently and are latched, DM
The time required to service A1 to 6 continuously may be longer than the set time. Here, if the lower priority requests do not rotate, the lower priority requests will be serviced while the lower priority requests will be serviced before the lower priority requests are serviced. It will be reset by the slice timer, leaving the relatively low priority request unserved.

However, if a request with a low priority is given rotation priority, a request with a relatively high priority at one time will have a low priority due to a rotation of the request, and a priority at a certain time. On the contrary, a request with a low priority will be serviced on average because the priority will eventually rotate and the priority will increase.

Next, another method for enabling access from the CPU without stopping the DMA transfer on the DMA signal bus side will be described in detail.

First, the configuration of the competition control circuit 12 will be described with reference to FIG.

This configuration is a configuration in which a priority order determination circuit 47 is added to the configuration of FIG. 6, and the access from the CPU gives priority to service other DMA requests. is there.

The requests from the respective request sources are latched by the latch circuits 41 and 42 at the same sampling clock, and the priority order is determined by the fixed priority circuit 43 and the rotation priority circuit 44, and then the service right circulation circuit 45. A DMA request having a service right is selected and processed. At this time, the priority determination circuit 47 recognizes the DMA bus access by the CPU, and if there is a request, gives priority to the access from the CPU and services it. If there is no request from the CPU, the service right is given. The DMA request selected by the circulation circuit 45 is directly serviced.

With respect to the operation of this embodiment configured as described above, FIG. 10 and FIG. 1 showing transition states of service right
The description will be given using the timing chart of No. 1.

FIG. 10 shows in what priority the latched request is serviced. (*) Means service right, and moves according to the overall priority determined by the priority of rotation priority. The service right (*) is not passed to the request that is not latched. Also, every time the slice timer times out, the service right (*) is forcibly transferred to the initial state DMA1. Also, if you latch the request,
The service right (*) is forcibly transferred to the initial state DMA1. However, even if the service right shifts to the initial state, the priority order of rotation priority retains that state.

In FIG. 11, DMAs 1 and 2 are high priority request sources, and DMAs 3 to 5 are low priority request sources. Then, the access request from the CPU is input to the priority determination circuit 47. The sampling of the service request state of each request source is always sampled when the latched request is not being serviced. However, S1 to S7 shown in FIG. And one service request is latched.

First, in FIG. 11, at first, only the request of DMA3 is active in the always sampling state, so this request is sampled and latched (S).
1). Then, the DMA 3 is serviced. Since the DMA3 is assigned as the low-priority request source, when the service ends, the priority order of the rotation priority shown in FIG. 10 is the next DM of the currently serviced DMA3.
A4 is the highest rank, and the priority status is (301). When the low priority request source is not serviced, the priority order of the rotation priority unit does not change.

Next, when the service of the DMA3 is completed, the request state of the request source is sampled (S2). At this time, since the request of DMA1 is active, DMA1 is serviced next. Further, since the slice timer has timed out during this service, the request latched after the service ends is reset and the request is resampled (S3). At this time, DMA2
Since the request of DMA4 and DMA4 is active, DMA2 and DMA4 are being serviced in this order according to the priority order. However, since there was a request from the CPU during the service of DMA2, the CPU was serviced before DMA4 was serviced.
Request is given priority, and the DMA4 is serviced after the CPU service is completed.
The priority status does not change after the service of DMA2, does not change after the service of CPU, and becomes (302) after the service of DMA4.

When the service of the DMA4 is completed, the request is sampled and latched again (S4). At this time, the requests of DMA1 and DMA5 are active, but since there is a request of the CPU, the CPU is serviced with the highest priority. During the service of that CPU,
Since the slice timer times out, the request state latched after the service of the CPU is reset, the request of the request source is sampled again, and the requests of DMA1 and DMA5 are latched (S5). Then, the service is provided from the DMA 1, but since there is a request from the CPU during the service, after the service of the DMA 1 is completed, the request from the CPU is given priority to the service, and then the service of the DMA 5 is provided.

After the service is completed, sampling is performed again (S6), and the requests of DMA1 and DMA3 are latched. However, since there is a request of the CPU, the service of the CPU is first provided. After that, the service is being performed from the DMA1 having a higher priority, but just after the CPU service is completed, the slice timer times out, so that the currently latched requests of DMA1 and 3 are reset, and the DMA1 is again performed. Requests 3 and 3 are resampled (S7). And DMA1 with a high priority
Will be serviced. Since there was a request from the CPU during the service, the CPU is serviced prior to the DMA 3 next.

As described above, the access request from the CPU is made independent of the requests of other request sources, and the priority determination circuit at the final stage gives priority to the service regardless of the priority of the other request sources. Therefore, even if the CPU is in service to another request source at the time of making an access request, if one service ends, the access request of the CPU is given priority even if the other service request is latched. Since the CPU does not wait for a time longer than one DMA bus cycle after requesting the access, even if the CPU is prioritized in such a manner, the CPU access is performed at regular intervals. It becomes possible to serve a fixed priority request that requires service within a certain period of time. Further, it goes without saying that even low-priority requests can be serviced on average.

In the above embodiments, the configuration in which the two buses of the CPU bus 1 and the DMA bus 2 are provided has been described as an example, but in the case where the CPU 4 and the DMA controller 6 alternately use one bus. Also, it is possible to apply the present invention.

[0082]

As described above, according to the present invention, the CPU
However, when accessing each device on the DMA bus side, the read / write control of the device is performed in the cycle of the DMA controller side to input / output data.
The time lag of the circuit operation is reduced and the circuit can operate efficiently, and even when the CPU accesses the DMA bus, the original DMA transfer is not delayed.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of an operation procedure of the computer system.

FIG. 3 is an explanatory diagram of a data transfer operation between various devices.

FIG. 4 is a flowchart showing an example of an operation procedure of the computer system.

FIG. 5 is a time chart showing an example of the operation of the computer system.

FIG. 6 is a block configuration diagram of a competition control circuit according to an embodiment of the present invention.

FIG. 7 shows a transition state of service right.

FIG. 8 is a timing chart showing an example of an operation procedure of the competition control circuit.

FIG. 9 is a block configuration diagram of a competition control circuit according to another embodiment of the present invention.

FIG. 10 shows a transition state of service right.

FIG. 11 is a timing chart showing an example of an operation procedure of the competition control circuit.

FIG. 12 is an explanatory diagram showing the operation of a conventional computer system.

FIG. 13 is a timing chart showing the operation of a conventional computer system.

[Explanation of symbols]

 1 CPU Bus 1a, 2a Address Bus 1b, 2b Data Bus 2 DMA Bus 3a, 3b Bus Buffer Circuit 3c Buffer & Latch Circuit 4 CPU 5 DMA Bus Request Circuit 6 DMA Controller 7, 11 Memory 8-10 I / O Device 12 Contention Control circuit 41, 42 Latch circuit 43 Fixed priority circuit 44 Rotation priority circuit 45 Service right circulation circuit 46 Slice timer circuit 47 Priority determination circuit

Claims (4)

[Claims] 1. A CPU signal bus used when the CPU accesses a specific device, and a DMA signal bus used when the DMA controller accesses another device. The CPU and the DMA controller. Means that each device performs read / write control at a specified cycle asynchronous with each other to input / output data, and
In the operating method of the computer system, where the PU uses the signal bus for DMA to access the other device as necessary, when the CPU accesses the other device, the regulation of the DMA controller side A method for operating a computer system, characterized in that read / write control is performed on a device at a cycle to input / output data. 2. The method for operating a computer system according to claim 1, wherein the CPU uses the read / write control function of the DMA controller when accessing the other device. 3. A DMA request is provided with a priority order, the priority order is divided into a fixed priority order and a rotation priority order, the presence or absence of the request is monitored while being sampled, and when the request is latched, the services are serviced in order according to the priority order. However, when the service is for the rotation priority request, the rotation priority priority is rotated after the service ends, while the latched request is cleared and resampled at regular intervals. A method of operating a computer system according to claim 1. 4. A signal bus access request for DMA of the CPU is made independent from other DMA requests, and when there is an access request of the CPU, the access of the CPU is serviced with priority and the access request of the CPU is issued. 4. The method of operating a computer system according to claim 3, wherein the other DMA request is serviced according to the priority order when there is no such request.