JPH08110887A - Common bus system - Google Patents

Abstract

PURPOSE: To provide a common bus system which consists of >=3 bus masters including microprocessors and can have an access to an unused memory in a short time. CONSTITUTION: The common bus system includes a 1st circuit 100 where a 1st bus master 10 is connected to a resources 11 via a 1st bus 41, a 2nd circuit 200 where a 2nd bus master 20 is connected to a common resources 21 via a 2nd bus 42, a 1st gate 51 which is placed between both buses 41 and 42, a 2nd gate 52 which is placed between a 3rd bus master 30 and the bus 41, a 1st bus conflict control part 60, and a 2nd bus conflict control part 70. In such a constitution, the bus master 10 consists of a microprocessor that contains a bus retry access function and the part 70 includes a retry signal generation circuit 71 which secures an AND between the access state set to the bus 42 and the access state of the microprocessor set to the bus 42 and outputs a retry signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common bus system composed of three or more bus masters including a microprocessor.

Usually, a microprocessor and a direct memory access controller (DirectMemory Access Controller)
In a common bus system in which there are three or more bus masters (hereinafter referred to as roller, DMAC)), each bus master outputs a bus request to the bus contention control circuit,
The bus master that receives the bus acknowledge is configured to use the common bus.

With the recent development of information processing apparatuses, the amount of information processed in the system is increasing, and it is required to transfer a large amount of data in the system in a short time. There is.

Direct memory access (Dire) is one of the methods for transferring such a large amount of data at high speed.
ct Memory Access, hereinafter referred to as DMA) system is adopted. Even if such a DMA method is used, bus contention occurs in a common bus system having three or more bus masters. Therefore, when bus contention occurs, the bus contention control circuit performs arbitration, but the processing speed decreases.

Even if such a bus conflict occurs,
There is a demand for a common bus system that arbitrates conflicts and does not reduce processing speed.

[0006]

2. Description of the Related Art FIG. 4 is a block diagram for explaining a conventional example. In the first circuit 100 in the figure, 10B is a microprocessor, 11A is a memory, and 41A is a microprocessor 1.
P bus connecting 0B and memory 11A, second circuit 200
20B is DMAC, 21A is memory, 42A is DM
B bus connecting the AC 20B and the memory 21A, 51A a gate connecting the P bus 41 and the B bus 42A, 30B a DMAC, 52A a gate connecting the DMAC 30B and the P bus 41A, 60A controlling contention of the P bus 41A A P bus contention control unit 70A is a B bus contention control unit that controls contention of the B bus 42A.

In this configuration, the memory 11A is a common resource between the microprocessor 10B and the DMAC 30B, and the memory 21A is a microprocessor 10B and the DMAC 20.
It is a common resource with B. Here, the microprocessor 10B has memories 11A, 21A, a DMAC 20B,
Since it is necessary to access all of 30B and bus contention occurs depending on the access state, a P bus contention control unit 60A and a B bus contention control unit 70A for arbitrating bus contention are provided.

For example, it is assumed that the DMAC 20B is accessing the memory 21A. The DMAC 20B has a high priority because it performs high-speed data transfer, and the memory 21A can be accessed at any time unless the microprocessor 10B is accessing the B bus 42A from the gate 51A. Microprocessor 10B is B bus 42
In order to acquire A, it is necessary to send a bus request to the B bus contention control unit 70A.
If B is not using the B bus 42A, a bus acknowledge is returned and the B bus 42A can be accessed. Therefore, the DMAC 20B waits for access to the B bus 42A only when the microprocessor 10B is accessing the B bus 42A.

On the other hand, the memory 11A is on the same P bus 41A as the microprocessor 10B, and the DMA
When the C30B accesses the memory 11A, the P bus contention control unit 60A notifies the microprocessor 10B of the P
A hold signal for holding the bus 41A is output.
After the bus cycle ends, the microprocessor 10B is held and the P bus 41A becomes empty.
The AC 30B can access the memory 11A.

[0010]

As described in the above-mentioned conventional example, the waiting mode of the microprocessor 10B is B.
Waiting (during bus cycle) is performed when accessing the bus 42A, and holding (between bus cycles) is performed when accessing the P bus 41A.

Therefore, the DMAC 20B has the B bus 42
If the microprocessor 10B tries to access the B bus 42A while accessing A, the microprocessor 10B enters the wait state, but the DMAC 30B sets P
Even if a bus request is issued in an attempt to access the bus 41A, the microprocessor 10B is in a bus cycle (waiting), so that the DMAC 30B is in the P bus 4
1A cannot be acquired and the memory 11A cannot be accessed.
Such a state is inaccessible even though there is no conflict in the memory 11A, and the occurrence of such a state reduces the processing speed. Therefore, it is required to be accessible when not used.

The present invention intends to realize a common bus system which makes it possible to access a memory which is not used and improve the system throughput.

[0013]

FIG. 1 is a block diagram for explaining the principle of the present invention. 100 is the first bus master 1
0 is the first circuit in which the first common resource 11 is connected to the microprocessor as 0, and 200 is the second bus master 20 and the second common resource 21 is connected to the second bus 42. A first gate provided between the first bus 41 and the second bus 42, and 52 provided between the third bus master and the first bus 41. 60 is the first bus 41
Is a first bus contention control unit, and 70 is a second bus contention control unit, which performs contention control of the second bus 42.

Reference numeral 71 is a retry signal generation circuit provided in the second bus contention control unit 70 according to the present invention.
Of the access state to the bus 42 and the access state of the microprocessor 10 having the retry access function to the second bus 42 are ANDed and output as a retry signal.

Further, the microprocessor as the first bus master 10 is composed of a microprocessor having a retry access function, and the second bus master 20 is the second.
When the microprocessor 10 with the retry access function accesses the second common resource 21 while accessing the common resource 21 of the above, the retry signal output from the retry signal generation circuit 71 causes the bus of the microprocessor with the retry access function. It is configured to end the cycle once.

[0016]

Most of recent microprocessors have a retry access function. In the present invention, such a microprocessor with a retry access function is used as the first bus master 10, and an access state to the second bus 42 output from the retry signal generation circuit 71 and a microprocessor with a retry access function are used. A retry signal obtained by ANDing access states of the processor to the second bus 42 temporarily terminates the bus cycle of the microprocessor with a retry access function, and the third bus master 30 accesses the first common resource 11. Accepts the bus request for the third bus master 30
Enable access to the first common resource 11.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a method for solving the problems of the conventional example, the following method can be considered. Before the microprocessor as the first bus master 10 accesses the second bus 42, it is checked whether or not it is empty, and if it is empty, the second bus master is temporarily stopped and then the second bus 42 is switched to. A method of accessing can be considered.

If this method is adopted, the access to the second bus 42 is immediately terminated, and the third bus master 30 waits for the time for the microprocessor to access the second bus 42, and then the first bus master 30 waits for the first access. It becomes possible to access the bus 41.

However, in such a system, hardware for checking whether the second bus 42 is empty is required, and since it is checked by using firmware whether the second bus 42 is empty or not. In addition, the microprocessor will perform the processing for that purpose, and the processing speed will decrease.
Also, since the second bus master 20 is temporarily stopped,
It is not a good solution because the data transfer rate between the second bus master 20 and the second common resource 21 also decreases.

Therefore, the present invention solves the problem by utilizing the retry access function generally provided in recent microprocessors. The retry access function is a function of executing the bus cycle just performed when the retry signal is output to the microprocessor at the end of the bus access, and the firmware does not intervene. (For example, when an error is detected as a result of reading a certain data and performing a parity check, the same data is read again.) FIG. 2 is a block diagram illustrating an embodiment of the present invention. In the figure, the first circuit 100 described in the principle diagram is composed of a microprocessor 10A with a retry function and a memory 11A, and the second circuit 200 is an HDLC (High-level Data Link).
Control procedure) 20A and memory 21A, and third bus master 30 is HDLC 30A.

The first bus 41 described in the principle diagram is also used.
Is constituted by a P bus 41A, and the second bus 42 is constituted by a B bus 42
A, the first and second gates 51 and 52 are composed of gates 51A and 52A, and the first and second bus contention control units 60 and 70 are P bus contention control units 60A and B bus contention control units. It consists of 70.

In the figure, HDLC 20A is for high speed, H
The DLC 30A is for low speed and has a serial interface (not shown). The DLC 30A writes received data from the serial interface to the memories 11A and 21A and sends data on the memories 11A and 21A to the serial interface. A DMAC function is provided to perform these transmission / reception processes at high speed. Reference numeral 61 in the P bus contention control unit 60A is a bus cycle end notification circuit (shown as a bus end notification circuit in the figure) for notifying that the bus cycle of the P bus 41A is completed, and the B bus contention control unit 70.
Reference numeral 72 in A is a bus cycle end notifying circuit for notifying that the bus cycle of the B bus 42A is completed.

The bus cycle end notification circuit 61 is the P bus 4
When the bus cycle of 1A ends, the bus cycle end signal is returned to the HDLC 30A to end the bus cycle. Until this bus cycle end signal is returned, H
The DLC 30A enters the wait state and the bus cycle does not end. Similarly, the bus cycle end notification circuit 72 outputs B
When the bus cycle of the bus 42A ends, the bus cycle end signal is returned to the HDLC 20A to end the bus cycle. The HDLC 20A enters the wait state until the bus cycle end signal is returned, and the bus cycle is not ended.

The retry signal generating circuit 71 is HDL.
A logical product of a signal indicating that the C20A is accessing the B bus 42A and a signal indicating that the microprocessor 10A with the retry function accesses the B bus 42A is ANDed and output to the microprocessor 10A with the retry function. Is.

FIG. 3 shows an access time chart of the embodiment of the present invention. In the figure, HDLC 20A is B bus 4
While accessing 2A, the microprocessor with a retry function (shown as μP in the figure) 10A has the B bus 4
Since a bus collision occurs when trying to access 2A, a retry signal is sent from the retry signal generation circuit 71, and the microprocessor 10A with a retry function is put in the retry state. Here, since the microprocessor 10A is in the hold state in the next bus cycle, the HD
The LC30A can access the P bus 41A,
The HDLC 30A data can be serially transmitted and received. Further, the μP retry bus access in the time chart shows that the microprocessor again performs the access operation to the B bus 42A by the retry signal.

6 is an access time chart of the conventional example of FIG. FIG. 5 shows the same time axis for comparison with the time chart of the embodiment of FIG. 3. When comparing FIG. 3 and FIG. 5, in the embodiment of the present invention of FIG.
On the 0A side, the processing ends one cycle earlier, so it can be seen that the data can be transmitted earlier during that time.

[0027]

According to the present invention, it is possible to reduce the waiting time when accessing when the memory on the P bus is not in contention, and to improve the throughput as a common bus system. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is an access time chart of the embodiment of the present invention.

FIG. 4 is a block diagram illustrating a conventional example.

FIG. 5 is an access time chart of a conventional example.

[Explanation of symbols]

 100 1st circuit 200 2nd circuit 10 1st bus master 10A, 10B Microprocessor 11 1st common resource 11A, 21A memory 20 2nd bus master 20A, 30A HDLC 20B, 30B DMAC 21 2nd common resource 30 3rd Bus master 41 First bus 41A P bus 42 Second bus 42A B bus 51 First gate 52 Second gate 51A, 52A Gate 60 First bus contention controller 60A P bus contention controller 70 Second Bus contention control unit 70A B Bus contention control unit 61, 72 Bus cycle end notification circuit 71 Retry signal generation circuit

Claims (1)

[Claims] 1. A common bus system to which three or more bus masters each including a microprocessor are connected, wherein a first circuit in which a first bus master and a first common resource are connected by a first bus, A second circuit in which a second bus master and a second common resource are connected by a second bus; and a first circuit provided between the first bus and the second bus.
Gate, a second gate provided between a third bus master and the first bus, a first bus contention control unit that performs contention control of the first bus, and the second bus In the common bus system including a second bus contention control unit for performing the contention control, the first bus master is configured by a microprocessor having a bus retry access function, and the second bus contention control unit includes a second bus master unit. A retry signal generation circuit that logically ANDs an access state of the bus to the bus and an access state of the microprocessor with the retry access function to the second bus, and outputs the logical product as a retry signal. When the microprocessor with a retry access function accesses the second common resource while accessing the second common resource, the retry signal generation is performed. The retry signal output from the circuit,
The bus cycle of the microprocessor with the retry access function is once terminated, the third bus master accepts a bus request for accessing the first common resource, and the third bus master receives the first common resource. A common bus system that is characterized by accessing.