JPH0573483A - Bus use right control method - Google Patents

Abstract

PURPOSE:To efficiently use a system bus by changing a data transfer of each input/output controller in accordance with a use state of the system bus, and eliminating generation of the input/output controller for waiting continuously for obtaining the bus use right for a long time. CONSTITUTION:Input/output controllers 15, 16 monitor the number of times of outputs of a bus use right request which cannot obtain the bus use right but is outputted repeatedly. In the case this number of times of outputs reaches a set value prepared in advance, a repeat period for repeating the output of the bus use right request is shortened, and the frequency for outputting the bus use right request is raised. Also, the input/output controllers 15, 16 monitor the number of times of obtaining the own bus use right in a unit time. In the case this number of times of obtaining reaches a set value prepared in advance, the repeat period for repeating the output of the bus use right request is lengthened, and the frequency for outputting the bus use right request is lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus usage right control method capable of avoiding a situation in which the system bus usage right is kept waiting for a long time.

[0002]

2. Description of the Related Art In a computer system containing a plurality of input / output devices such as a magnetic storage device and a printer, bus arbitration is performed in order to realize efficient use of a system bus.

This arbitration is carried out by a bus control unit provided in the computer system. The bus controller is
A bus use right request that is output to request the use of the system bus is accepted, arbitration is performed when the requests are duplicated, and the bus use right is given to only one of the requests. If there is only one request without duplication, the bus usage right is immediately given to the device that has output the bus usage right request without arbitration. Here, the process until the bus usage right is granted based on the bus usage right request will be referred to as a system bus usage right control method.

FIG. 2 shows a block diagram of a conventional general computer system. In the computer system 1 shown in the figure, the processor (CPU) 2 is connected to the main storage device (MM) 3, the bus control unit 4, the first to nth input / output control devices (IOC # 0) via the system bus SB. ~ #N) 5
~ 7 are connected. First to nth input / output devices (IO # 0 to #N) 8 to 10 are connected to the respective input / output control devices.

The processor 2 is a computer system 1.
It controls each part constituting the. The main storage device 3 is a RAM that stores programs and data referred to by the processor 2, and further processing results by the processor 2.
And the like. The bus control unit 4 performs control for granting the bus use right to any of the input / output control devices based on the bus use right request output from each input / output control device.

The first to nth input / output control devices 5 to 7 are connected to the system bus SB and the first to nth input / output devices 8 to 10, respectively.
It controls the data transfer between the two and outputs the bus use right request and acquires the bus use right.

A unique data transfer rate is set for each of the first to nth input / output control devices 5-7.
Data transfer between each input / output device and the system bus SB is performed at this data transfer rate. The data transfer rate is set in advance according to the usage efficiency of the system bus SB, the importance of each input / output device, and the like. Each I / O controller
By setting the data transfer rate below the originally provided performance, the data transfer rate (priority) can be differentiated.

Further, when the bus use right cannot be acquired as a result of outputting the bus use right request, the first to nth input / output control devices 5 to 7 output a new bus use right request. The cycle is set similarly to the data transfer rate. Here, it is assumed that the higher the data transfer rate, the shorter the repetition period is set, and the bus usage right request can be output more frequently.

The first to nth input / output devices 8 to 10 are composed of, for example, a magnetic storage device, a printer or the like.
~ Data transfer to / from the system bus SB is realized by the control of the nth input / output control devices 5 to 7. For example, the first input / output control device 5 that receives the data transfer instruction from the processor 2 transfers the data received from the input / output device 8 to the system bus SB at the data transfer rate set in the first input / output control device 5. It is transferred to the main storage device 3 via the. The transfer destination is
The same applies to other input / output control devices (input / output devices) instead of the main storage device 3.

A description will be given of the method of controlling the system bus use right in the computer system 1 having the above configuration with reference to FIGS. 3 and 4. FIG. 3 is a first explanatory diagram according to the conventional method. As shown in the figure, when data transfer is performed, one cycle is used for the arbitration cycle S for acquiring the bus use right of the system bus SB, and a data transfer cycle for actually transferring data using the system bus SB. At least three cycles are required, one cycle for T and one cycle for the termination cycle R for relinquishing the bus use right. If the bus usage right cannot be acquired at the same time as the bus usage right request is output, the bus usage right request is repeatedly output, and the time required to carry out the data transfer becomes longer.

FIG. 4 is a second explanatory view according to the conventional method. As shown in the figure, when the bus use right cannot be acquired immediately after the bus use right request is output, the arbitration cycle S becomes long (n cycles) to repeatedly output the bus use right request, and one data transfer is performed. N + 2 cycles are required to carry out.

The arbitration cycle S, the data transfer cycle T, and the termination cycle R may be pipelined. FIG. 5 shows a third explanatory view according to the conventional method. The figure shows a state in which data transfer is sequentially performed using the system bus SB from a state where the system bus SB is not used.

First, the first input / output control device 5 executes the arbitration cycle Sn (first
Cycle), and thereafter, the data transfer cycle Tn (second cycle) and the termination cycle Rn (third cycle) are 1 respectively.
It is assumed that the cycle time is spent.

When the second input / output control device 6 executes the arbitration cycle Sn + 1 in the second cycle, the input / output control device 5 is executed in the third and fourth cycles.
Similarly, data transfer cycle Tn + 1 and termination cycle Rn
+1 is executed.

Further, in the third cycle, when the nth input / output control unit 7 executes the arbitration cycle Sn + 3, the data transfer cycle and the termination cycle are similarly executed thereafter. In the second and subsequent cycles, so-called pipeline processing, in which the arbitration cycle, the data transfer cycle, and the termination cycle are processed in parallel, is executed, and the usage efficiency of the system bus SB can be improved.

[0016]

In the conventional input / output control device, since the repetition cycle for outputting the bus use right request is fixedly set, in the computer system 1 in which the system bus SB is frequently used, However, there has been a problem that it is difficult to grant the bus use right to the input / output control device having a long repetition period. Further, when any one of the input / output control devices (input / output devices) is deleted (degenerated) from the computer system 1, the use efficiency of the system bus SB is reduced, but the data transfer of the remaining input / output control device is performed. There has been a problem that the speed cannot be changed to improve the efficiency of use of the system bus SB. Further, when the pipeline processing is to be executed, each input / output control device needs to complete the arbitration cycle in one cycle. However, the bus usage right cannot be acquired by one bus usage right request, and if a plurality of cycles are spent in the arbitration cycle, there is a problem that one data is not completed in three cycles and the pipe is disturbed. .. The present invention has been made paying attention to the above points, and the cycle of repeatedly outputting the bus usage right request of each input / output control device is changed according to the usage status of the system bus to acquire the bus usage right for a long time. It is an object of the present invention to provide a more bus use right control method capable of eliminating the occurrence of an I / O controller which keeps waiting and realizing efficient use of a system bus.

[0017]

SUMMARY OF THE INVENTION A bus use right control method according to the present invention includes a system bus, a plurality of input / output devices for transferring data using the system bus, and a bus use right of the system bus. A bus control unit that performs arbitration and an input / output control device that is provided for each of the input / output devices and that outputs a bus use right request for acquiring the bus use right of the system bus to the bus control unit. When any one of the input / output devices acquires the bus use right as a result of outputting the bus use right request to each of the input / output control devices, the acquisition of the bus use right is awaited and a new A request cycle for outputting the bus usage right request is set, and the number of times of waiting for the bus usage right that continuously occurs is counted for each of the input / output control devices, and the number of times of waiting is set to a preset value. What said The request cycle of Kano output control unit shorter, increase the frequency of outputting the bus request of the input-output control unit. A system bus, a plurality of input / output devices that transfer data using the system bus, a bus control unit that arbitrates the bus use right of the system bus, and the input / output devices are provided for each of the input / output devices. And an input / output control device for outputting a bus use right request for acquiring the bus use right of the system bus to the bus control unit, and each of the input / output control devices is provided with the bus use right request. When any one of the input / output devices acquires the bus use right as a result of the output, it waits for the acquisition of the bus use right and sets a request cycle for newly outputting the bus use right request, For each output control device, the number of times the bus usage right is acquired per preset unit time is monitored, and the request cycle of any one of the input / output control devices in which the number of acquisitions reaches a preset set value. Lengthen Reduce the frequency for outputting the bus request of the input-output control unit.

[0018]

According to this method, as a result of the output of the bus use right request from the I / O controller, the bus use right cannot be acquired, and the number of waiting times for waiting for the acquisition of the bus use right is monitored. When the number of waiting times reaches a preset set value, the cycle of repeating the output of the bus use right request is shortened and the frequency of outputting the bus use right request is increased. Further, the input / output control device monitors the number of times of acquisition of its own bus use right per unit time.
When the number of acquisitions reaches a preset set value, the repetition cycle for repeating the output of the bus use right request is lengthened and the frequency of outputting the bus use right request is reduced.

[0019]

1 shows a block diagram according to a first embodiment of the present invention. In the computer system 11 shown in the figure, the system bus SB has a processor (CPU) 1
2, a main memory device (MM) 13, a bus control unit 14, a first input / output control device (IOC # 0) 15, and an nth input / output control device (IOC # N) 16 are connected. First and nth input / output devices 17 and 18 are connected to the first and nth input / output control devices 15 and 16, respectively.

The processor 12, the main memory 13, the bus controller 14, and the first and nth input / output devices 17, 18
Is the processor 2, the main storage device 3, the bus control unit 4, the first and nth input / output devices 8 and 1 described above with reference to FIG.
It is the same as 0. Therefore, redundant description will be omitted.

The first input / output control device 15 includes an arbitration monitoring unit 21, a waiting count detecting unit 22, and a masking unit 2.
3, a counting unit 24, a setting unit 25, a comparison unit 26, and a transfer speed setting unit 27 are provided. Aviation monitoring unit 2
1 is for monitoring how many cycles the system bus SB has been used for one data transfer (from the arbitration cycle to the end cycle).

The number-of-waiting detection unit 22 determines whether the number of cycles detected by the arbitration monitoring unit 21 exceeds three cycles, that is, because one of the input / output control devices uses the system bus SB, the right to use the bus. Is detected, that is, the number of times of waiting. Mask part 23
Is for setting whether or not the operation of the waiting number detecting unit 22 is enabled. The counting unit 24 uses the waiting frequency detection unit 22.
It is composed of a register or the like for storing the detection result of. The setting unit 25 is composed of a register or the like that stores an allowable value of the number of waits detected by the number-of-waits detection unit 22.

The comparison unit 26 compares the contents of the setting unit 25 and the contents of the counting unit 24. Transfer rate setting unit 27
Receives the comparison result of the comparison unit 26 and changes the preset data transfer rate. These configurations are the same for other input / output control devices.

In the computer system 11 having the above configuration, the data transfer rate of the nth I / O controller 16 is "100" and the data transfer rate of the first I / O controller 15 is "50". That is, the nth input / output control device 16
This means that the data transfer rate is twice as high as that of the first input / output control device 15. Further, it is assumed that both the first and nth input / output devices 15 and 16 have a data transfer rate of “200”. That is, the data transfer rate set for actual operation is a value with reduced capability.

Now, the first and nth input / output control devices 15,
When 16 bus usage right requests conflict, the bus control unit 14
Is given the right to use the bus to the nth input / output control device 16,
The first input / output control device 15 waits for the timing of newly outputting the bus use right request. In the first input / output control device 15,
It is assumed that the n-th input / output control device 16 executes a termination cycle before the timing of outputting a new bus use right request arrives and further starts using the system bus SB based on a new arbitration cycle. ..

Here, even if the first input / output control unit 15 outputs a new bus use right request, the system bus SB is already used by the nth input / output control unit 16, so that a new timing is set. I will wait for the arrival. During this period, the arbitration monitoring unit 21 detects the number of cycles required for one data transfer. Waiting frequency detection unit 22
Increases the value of the counter 24 when the detection result of the arbitration monitor 21 exceeds 3 cycles.

The comparison unit 26 sequentially compares the contents of the setting unit 25 and the contents of the counting unit 24, and the contents of the counting unit 24 is set to the setting unit 2.
When the content of 5 is exceeded, the transfer rate setting unit 27 is activated. In the activated transfer rate setting unit 27, the data transfer rate is changed from “50” to “150”, and the counting unit 2
4 is reset. As the data transfer rate increases,
The input / output control device 15 outputs the bus use right request at a shorter cycle than when the data transfer rate is “50”.

When the cycle is shortened, the probability of outputting the bus right request after the termination cycle is increased, and the priority is improved as the data transfer rate is increased. Therefore, even if it competes with the nth I / O controller 16. You can get the right to use the bus. When the bus right is acquired by changing the data transfer rate and the termination cycle is executed, the I / O controller 15 returns the data transfer rate to "50" again and shifts to the basic operating state.

FIG. 6 shows a first flow chart according to the present invention. When the computer system 11 is activated, the processor 12 gives an instruction to initialize the transfer rate setting unit 27 provided in each input / output device, and sets a unique data transfer rate for each (step S1). Further, the processor 12 sets an arbitrary value in the setting unit 25 provided in each input / output device (step S2). Finally, the processor 12 uses the mask unit 23 provided in each input / output control device.
The masking function of 2 is released, and the waiting number detecting unit 22 is enabled (step S3).

After that, the arbitration monitoring unit 21 monitors the system bus SB and notifies the waiting count detection unit 22 of the monitoring result (step S4). Waiting frequency detection unit 2
In 2, the presence / absence of the number of waits is determined based on the notification from the arbitration monitoring unit 21 (step S5). If the result is YES, that is, the number of waits is present, the counting unit 24 counts up (step S6). ..

The comparison unit 26 compares the value of the setting unit 25 with the value of the counting unit 24 (step S7), determines whether the value of the counting unit 24 exceeds the contents of the setting unit 25, and determines the determination result as the transfer rate. The setting unit 27 is notified (step S8). If the result of step S8 is YES, the transfer rate setting section 27 changes the previously set data transfer rate to increase the speed (step S9), and clears the value of the counting section 24 (step S10).

After performing step S10, and step S
If NO is determined in S5 and S8, the process returns to step S4. In this case, by increasing the bus usage right acquisition capability of an input / output device that keeps waiting for the use of the system bus SB for a long time, a specific input / output control device is given an environment in which the system bus SB can be preferentially used. be able to.

Next, a second embodiment according to the present invention will be described. FIG. 7 shows a block diagram according to the second embodiment of the present invention. In the computer system 31 shown in the figure, the counting unit 24 of the first input / output control device 15 is different from that of the computer system 11 previously described in FIG.
Further, a bus monitoring unit 32 is provided instead of the arbitration monitoring unit 21, and an operation number detection unit 33 is provided instead of the waiting number detection unit 22.

The bus monitor 32 monitors the occurrence of an arbitration cycle on the system bus SB. The operation number detection unit 33 counts the number of times the bus monitoring unit 32 has performed the monitoring result per unit time, that is, the number of times it has performed itself in the arbitration cycle.

In the computer system 31 having the above configuration, the data transfer rate of the nth I / O controller 16 is "100" and the data transfer rate of the first I / O controller 15 is "50". That is, the nth input / output control device 16
This means that the data transfer rate is twice as high as that of the first input / output control device 15. Further, it is assumed that both the first and nth input / output devices 15 and 16 have a data transfer rate of “200”. That is, the data transfer rate set for actual operation is a value with reduced capability.

Now, the first and nth input / output control devices 15,
When 16 bus usage right requests conflict, the bus control unit 14
Grants the bus right to the nth input / output control unit 16,
The input / output control device 15 waits for the timing of newly outputting the bus use right request.

Since the n-th input / output device 16 has a short cycle of outputting a bus use right request, that is, a cycle of executing an arbitration cycle, it frequently arbitrates as long as data transfer using the system bus SB is required. Carry out a cycle. Then, the shorter the cycle in which the arbitration cycle is executed, the higher the probability of acquiring the bus use right. Therefore, the usage rate of the system bus SB by the nth input / output device 16 per unit time increases.

During this period, the bus monitoring unit 32 detects the occurrence of the arbitration cycle and notifies the operating frequency detecting unit 33 of the occurrence. The operation number detection unit 33 notifies the comparison unit 26 of the number of times per unit time that the operation unit itself has performed in the arbitration cycle. The comparison unit 26 compares the notified number with the value of the setting unit 25, and when the notified value exceeds the value of the setting unit 25, activates the transfer speed setting unit 27.

The activated transfer rate setting unit 27 changes the data transfer rate from "100" to "30", for example.
When the data transfer rate decreases, the input / output control device 15 outputs the bus use right request at a longer cycle than when the data transfer rate is "100".

When the cycle becomes long, the probability of outputting the bus use right request after the termination cycle is lowered, and the priority is also lowered as the data transfer rate is lowered. Therefore, the nth I / O controller 16 and the first I / O controller 16 are connected. When the control devices 15 compete with each other, the bus right is given to the first input / output control device 15. When the input / output control device 16 detects that the bus use right is given to another input / output control device due to the change of the data transfer rate, the input / output control device 16 returns the data transfer rate to "100" again,
Move to basic operating state.

FIG. 8 shows a second flowchart according to the present invention. When the computer system 31 is activated, the processor 12 gives an instruction to initialize the transfer rate setting unit 27 provided in each input / output device, and sets a unique data transfer rate (step S11). Further, the processor 12 sets an arbitrary value in the setting unit 25 provided in each input / output device (step S12). Finally, the processor 12 cancels the masking function of the masking unit 23 provided in each input / output control device and activates the operation number detecting unit 33 (step S13).

After that, the bus monitoring unit 32 sets the system bus SB.
Is monitored and the monitoring result is notified to the operation number detection unit 33 (step S14). The operating frequency detection unit 33 determines whether or not the system bus SB is used based on the notification from the bus monitoring unit 32 (step S15), and the result is YE.
S, that is, when the arbitration cycle is performed, the operation number detection unit 33 counts the number of times the system bus is used by itself per unit time (step S16),
The comparison result is notified to the comparison unit 26.

The comparison unit 26 compares the notification content with the value of the setting unit 25 (step S17), and the notification content is determined by the setting unit 25.
It is determined whether or not the value exceeds the value of, and the determination result is notified to the transfer rate setting unit 27 (step S18). When the result of step S18 is YES, the transfer rate setting unit 27 changes the previously set data transfer rate to reduce the speed (step S19), and resets the operation number detection unit 33, that is, clears the operation number. Is performed (step S20).

After performing step S20, and step S
If NO is determined in S15 and S18, the process returns to step S14. In this case, by reducing the frequency of use of the input / output control device that frequently uses the system bus SB, it is possible to increase the chances that another input / output control device will use the system bus SB.

The present invention is not limited to the above embodiments. In the embodiment, the case where the data transfer rate is changed by the entry / exit control device itself has been described as an example, but only the transfer rate setting unit 27 is installed in the input / output control device, and other configurations are provided in the bus control unit 1.
4 or provided in the processor 12.
When the bus control unit 14 is provided with a configuration other than the transfer rate setting unit 27, it is possible to envisage a case of directly controlling the transfer rate setting unit 27 and a case of controlling the transfer rate setting unit 27 via the processor 12. ..

[0046]

As described above, when the number of waits in which the bus usage right cannot be acquired reaches the set value as a result of the output of the bus usage right request, the repetition cycle for outputting the bus usage right request is shortened. The frequency of outputting the bus usage right request increases, and the probability of acquiring the bus usage right also increases. Further, when the bus usage right acquisition frequency per unit time reaches the set value, the repetition cycle of outputting the bus usage right request is lengthened, so that the frequency of outputting the bus usage right request decreases and the bus usage right is acquired. The probability of establishment also declines. As a result, it is possible to prevent the centralized bus use right acquisition and the centralized bus use right wait by any one of the input / output control devices, and each input / output device acquires the bus use right evenly. You can Therefore, even when the pipeline processing is performed, the plurality of input / output control devices can smoothly acquire the bus use right, and it is possible to prevent the disturbance of the pipe.

[Brief description of drawings]

FIG. 1 is a block diagram according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional general computer system.

FIG. 3 is a first explanatory diagram according to a conventional method.

FIG. 4 is a second explanatory diagram according to a conventional method.

FIG. 5 is a third explanatory diagram according to the conventional method.

FIG. 6 is a first flowchart according to the present invention.

FIG. 7 is a block diagram of a second embodiment according to the present invention.

FIG. 8 is a second flowchart according to the present invention.

[Explanation of symbols]

 21 arbitration monitoring unit 22 waiting number detecting unit 23 masking unit 24 counting unit 25 setting unit 26 comparing unit 27 transfer rate setting unit 32 bus monitoring unit 33 operating number detecting unit

Claims (2)

[Claims] 1. A system bus, a plurality of input / output devices for transferring data using the system bus, a bus control unit for arbitrating bus usage rights of the system bus, and each of the input / output devices. And an input / output control device for outputting a bus use right request for acquiring the bus use right of the system bus to the bus control unit, and each of the input / output control devices is provided with the bus use right. As a result of outputting the right request, when any one of the input / output devices acquires the bus use right, it waits for the acquisition of the bus use right,
A request cycle for newly outputting the bus use right request is set, and the number of times of waiting for the bus use right that continuously occurs is counted for each of the input / output control devices, and the number of times of waiting is set in advance. A bus use right control method, characterized in that the request cycle of any one of the input / output control devices that has reached a value is shortened and the frequency of outputting the bus use right request of the input / output control device is increased. 2. A system bus, a plurality of input / output devices for transferring data using the system bus, a bus control unit for arbitrating bus usage rights of the system bus, and each of the input / output devices. And an input / output control device for outputting a bus use right request for acquiring the bus use right of the system bus to the bus control unit, and each of the input / output control devices is provided with the bus use right. As a result of outputting the right request, when any one of the input / output devices acquires the bus use right, it waits for the acquisition of the bus use right,
A request cycle for newly outputting the bus usage right request is set, and the number of times the bus usage right is acquired for each preset unit time is monitored for each input / output control device. A method of controlling the bus use right, wherein the request cycle of any one of the input / output control devices that has reached the set value is lengthened, and the frequency of outputting the bus use right request of the input / output control device is reduced. ..