JP2003016024A - Apparatus for memory control and lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus for memory control capable of adjusting memory access contention by ensuring with necessary time accuracy required transfer rates to each bus master. SOLUTION: When transfer rate information determining the rates and time intervals to define ranges to maintain the rates regarding respectively to bus masters A-C needed to transfer data between a unified memory 200 is written into a storage part 111 for information transfer rate from a storage device outside of an LSI 100, a generating means 112 for timing information determines the shortest time interval as a period and calculates every bus master based on memory bus bands necessary times to secure the rates for each period to determine as approved times for use of buses. An adjusting part 114 adds sequentially within each period with a lapse of time rights for use of the buses only worth of the corresponding approved times to all bus masters requiring bus requests.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling memory access, and particularly to an LSI (large).
e scale integrated circuit
t) A memory control device included in the inside of the LSI, which relates to a memory control device for controlling access to a memory connected to the outside of the LSI by a plurality of circuits inside the LSI.

[0002]

2. Description of the Related Art In recent years, one or a plurality of DSPs (Digital Signal Proc) have been used for high-speed processing of video, audio, etc. against the backdrop of multimedia information.
essor), MPU (Microprocessin)
LSIs including g Unit) have been developed.

In addition to the MPU, a complex and high-performance LSI equipped with independent circuits such as a graphics processor, an AV (Audio Visual) decoder, and a hard disk controller has been developed. Each internal circuit in such a composite LSI is an independent circuit that can perform arithmetic processing for realizing each function by using an independent local memory, but each circuit uses the same memory. If the LSI is configured so as to share the arithmetic processing and the like for realizing the respective functions, it is possible to reduce the component cost.

To this end, it is necessary to provide a memory control device inside the LSI for arbitrating the competition of memory access by each circuit to the same memory. The memory control device arbitrates a memory access request from a plurality of circuits such as DSP and MPU (hereinafter referred to as “bus master”), that is, a bus request for a memory bus, and only one bus master at a certain time. Allow access. That is, the memory control device is
The bus use right of the memory bus is given to only one bus master.

On the other hand, each bus master issues a bus request to the memory control device when a memory access is required, and when it acquires the bus use right, it uses the memory bus to transfer data to and from the memory. . By the way, some bus masters need to transfer data at a constant transfer rate when there is data to be continuously processed in order to realize, for example, real-time reproduction of video and audio.

A bus master that requires data transfer at a constant transfer rate takes a time within which the transfer rate should be maintained due to the size of the internal input / output buffer, the data processing method, and other factors. It has its own requirements for spacing. For example, when viewed through 2 milliseconds (ms), 500 kilobytes / millisecond (K
B / ms), it is sufficient for some bus masters to maintain the transfer rate, while there is no time margin for securing the transfer rate, and 500 KB / ms for 1 ms.
For some bus masters, the transfer rate must be maintained.

If the memory can be monopolized,
Basically, the bus master repeatedly issues a bus request with a time interval within which the transfer rate should be maintained. Hereinafter, the time interval within which the transfer rate should be maintained is referred to as a bus request cycle. When designing an LSI that includes a plurality of bus masters that request data transfer at a constant transfer rate and a memory control device, the arbitration of the memory control device is performed in consideration of the transfer rate and the bus request cycle required by each bus master. The mechanism has to be built.

If arbitration is appropriate, each bus master can transfer data at the transfer rate requested, but if arbitration is not appropriate, the transfer rate required by any bus master within the bus request period. Therefore, there arises a problem that data transfer cannot be performed. Generally, conventional memory control devices include a arbitration mechanism that uses a bus use right preemption priority method and an arbitration method that arbitrates based on a priority determined for each bus master.

[0009]

The problems of such a conventional memory control device will be described below. Assuming that the bus bandwidth of the memory bus is about 800 KB / ms,
When there is data to be processed continuously, the bus request cycle is 2 ms and 1000 K is in the 2 ms.
A bus master A requesting to transfer the data of B;
Assume that the LSI includes two bus masters, a bus master B having a time margin of 1 ms and a bus request cycle of 1 ms, and a bus master B requesting to transfer 100 KB of data in the 1 ms. Further, it is assumed that the bus master A issues a bus request first if it is the preemption priority method, and that the bus master A has a high priority if it is the method of arbitrating based on the priority.

In this case, when the conventional memory control device receives a bus request from the bus master A, the memory control device gives the bus master A a bus use right to permit data transfer. In response to this, the bus master A 1000
Since it takes 1 ms or more to transfer the KB data, the memory control device cannot immediately respond to the bus request from the bus master B every 1 ms.

Therefore, the waiting time for memory access for the bus master B becomes longer than 1 ms,
The data transfer amount between the bus master B and the memory is 1 ms.
It is not unified to 100 KB in each cycle of the unit, and uneven transfer occurs. That is, the transfer rate required by the bus master B cannot be maintained within the bus request cycle.

As described above, the conventional memory control device having the arbitration mechanism using the bus use right preemption priority method or the arbitration method based on the priority guarantees the transfer rate required by each bus master in the long term. However, there is a problem that the transfer rate cannot be guaranteed in a short period of time. To solve this problem,
It is necessary to design the memory control device in consideration of the transfer rate required by each bus master, the time interval within which the transfer rate should be guaranteed, and the like.

However, the content of the processing required by each bus master changes depending on the device in which the LSI is mounted, and the transfer rate and bus request cycle required by each bus master change accordingly. It is difficult to design the memory control device in consideration of the specific processing contents of each bus master in advance. Also, year by year LS
Since I is highly functional, from the viewpoint of suppressing the development cost when a new circuit is incorporated in the LSI in the future, the data transfer rate of each circuit can be guaranteed regardless of the circuit included in the LSI. Design and development of such a versatile memory control device is required. This is because if the memory control device has high versatility, its design assets can be utilized for a long time.

Therefore, the present invention has been made in view of such a demand, and is a general-purpose technique for arbitrating contention of memory access by guaranteeing a required transfer rate to each bus master with necessary time accuracy. An object is to provide a memory control device. Another object is to provide an LSI including the memory control device and the bus master.

[0015]

In order to achieve the above object, a memory control device according to the present invention selectively grants a right to use a memory bus to any of a plurality of bus masters sharing a memory. Is a memory control device that arbitrates access competition to the memory by guaranteeing that, for each of a plurality of bus masters, the transfer rate at which the bus master transfers data to and from the memory and that the transfer is performed at the transfer rate Holding means for holding transfer rate information indicating a time interval defining a range to be performed, unit time calculating means for defining a time equal to or smaller than the smallest of the time intervals corresponding to each bus master as a unit time,
For each bus master, when the amount of data that can be transferred in the unit time according to the corresponding transfer rate is V, the bus use permission time that is the time required for V transfer based on the bus bandwidth of the memory bus is obtained. In the calculating unit and in each of a plurality of unit time zones obtained by periodically dividing the elapsed time by the unit time, a right of use for granting a right of use of the memory bus to each bus master for a corresponding bus use permission time And providing means.

Further, the memory control device according to the present invention is
A memory control device that arbitrates access competition to a memory by selectively granting a right to use a memory bus to a plurality of bus masters that access mutually independent memory areas in one memory. A holding unit that holds transfer rate information indicating a transfer rate when the bus master transfers data to and from the memory and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate. A unit time calculating means for setting a time equal to or smaller than the smallest one of the time intervals corresponding to each bus master as a unit time, and for each bus master, V is a data amount that can be transferred in the unit time according to a corresponding transfer rate. Based on the bus bandwidth of the memory bus, the time required for V transfer is the bus license. In each of a plurality of unit time zones obtained by periodically dividing the elapsed time into the unit time, the bus use permission time calculating unit for obtaining the time, and for each bus master, the bus use permission time corresponding to the corresponding bus use permission time And a usage right granting means for granting a usage right.

With the above configuration, even if there is no uniformity in the conditions regarding the transfer rates required by the respective bus masters, the transfer rates of the bus masters are satisfied so that the conditions concerning the transfer rates of the bus masters with the minimum transfer waiting margin can be satisfied. Since the adjustment is performed, it becomes possible for each bus master to perform data transfer while keeping the transfer rate constant with required time accuracy.

Further, by using this memory control device, even when the condition regarding the transfer rate of each bus master needs to be changed, the stored transfer rate information is simply rewritten to meet the request of each bus master. It becomes possible for each bus master to transfer data to and from the memory at the transfer rate. From this, it can be said that this memory control device can be utilized even if the bus master that is the target of access conflict control is replaced.

Further, the LSI according to the present invention arbitrates access competition to the memory by selectively granting the right to use the memory bus to a plurality of circuits sharing the memory and the plurality of circuits. An LSI including a memory control device, and the circuits are circuits that require data to be transferred at a constant transfer rate to and from the memory. A holding unit that holds transfer rate information indicating a transfer rate when the circuit transfers data to and from the memory and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate, and each circuit. Unit time calculating means for determining a time equal to or smaller than the smallest one of the time intervals corresponding to the unit time, and the unit time according to the corresponding transfer rate for each circuit. When the amount of data that can be transferred to V is V, bus usage permission time calculating means for determining a bus usage permission time that is the time required for V transfer based on the bus bandwidth of the memory bus, and the unit of time elapsed periodically. In each of multiple unit time zones obtained by dividing by time,
Each circuit is provided with a usage right granting means for granting a usage right of the memory bus for a corresponding bus usage permission time.

With the above structure, each of the plurality of internal circuits of the LSI can transfer data to and from the shared memory with the required transfer rate at the required time accuracy.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An LSI including a memory control unit and a plurality of bus masters, which is an embodiment of a memory control device according to the present invention, will be described below. <First Embodiment><Configuration> FIG. 1 is a configuration diagram of an LSI 100 including a memory control unit according to a first embodiment of the present invention. Note that FIG. 1 shows a unified memory 200 in addition to the LSI 100.

The LSI 100 is an LSI mounted on information home appliances and other devices, and includes a memory controller 110,
A bus master A 121, a bus master B 122, a bus master C 123, and a clock generator 190 are provided and are connected to the unified memory 200. Although not shown in FIG. 1, the LSI 100 is also connected to other external devices.

Here, the clock generator 190 is
The clock signal is sent to the memory control unit 110 and the bus masters A to C.
And a circuit to be supplied to the unified memory 200.
The bus masters A121, B122 and C123 use, for example, the unified memory 200 as a main memory.
A PU or a DSP that stores image data and the like in the unified memory 200, and independently accesses the unified memory 200 to perform data transfer. That is, each of the bus masters A to C issues a bus request to the memory control unit 110 through the REQ signal line when data transfer is required, obtains the bus use right from the memory control unit 110 through the GNT signal line, and The arbitration unit 1 of the memory control unit 110 at a timing based on the clock signal from the clock generator 190 while obtaining the usage right.
Data is transferred in synchronization with 14.

In FIG. 1, the bus requests from the bus masters are REQ-A, REQ-B and REQ, respectively.
-C, and GNT-A, GNT-B, and GNT-C represent the granting of the bus use right to each bus master. In addition, data transfer is performed by specifying the memory address and
By writing data to the unified memory or reading data from the unified memory,
As a result, the address and the data are transmitted on the memory bus. The data transferred between each bus master and the unified memory 200 is, for example, video data generated by the bus master based on the data input from the external device and output to the display device.

Each bus master independently performs a data transfer process. For example, in order to prevent the video output to the display device from being interrupted, for example, the bus master and the unified memory have a fixed transfer rate. The data must be transferred. However, the bus master does not always continuously perform data transfer with the unified memory. For example, the bus master continuously transfers data to the unified memory during the period in which the data to be sent is generated and accumulated due to continuous input of data from the external device. Is not input, the bus master does not transfer data to the unified memory during a period in which data to be transmitted is not accumulated.

The memory control unit 110 arbitrates the access to the unified memory 200 of each bus master based on the transfer rate information transmitted from the external device, and the transfer rate information storage unit 111 and the timing information generation unit. It has a unit 112, a timing information storage unit 113, and an arbitration unit 114. Here, the transfer rate information storage unit 11
Reference numeral 1 is a memory area for storing transfer rate information transmitted from an external device. The transfer rate information will be described later in detail.

The timing information generation unit 112 has a function of referring to the transfer rate information stored in the transfer rate information storage unit 111 to generate timing information and storing it in the timing information storage unit 113. The timing information will be described later in detail. The timing information storage unit 113 is a memory area for storing timing information.

The arbitration unit 114 includes the timing information storage unit 1.
13, the presence / absence of a bus request from each bus master is checked at a predetermined timing based on the clock signal from the clock generator 190, and the bus master issuing the bus request is selectively and sequentially selected. It has the function of giving the right to use the bus. Each bus master issues a bus request to the arbitration unit 114 by activating the REQ signal line, and the arbitration unit 114 grants the bus use right to the bus master by activating the GNT signal line to any of the bus masters. The bus master keeps the REQ signal line active as long as data transfer is necessary.

<Data> FIG. 2 is a diagram showing a data structure and an example of contents of the transfer rate information stored in the transfer rate information storage unit 111 transmitted from an external device. As shown in the figure, the transfer rate information 300 includes bus masters A to
About C, it is the information which matched the group of the request period 302 and the data transfer amount 303 of 1 time. The transfer rate information may be, for example, a memory and a CP provided outside the LSI.
Each bus master in the LSI is controlled by the unified memory 2 by an external device or the like that includes U and controls the LSI 100.
It is set before accessing 00 to start the processing involving data transfer.

Here, the request period 302 is a time interval within which the transfer rate required by each bus master when there is data to be continuously processed is within a range to be maintained. When there is data to be continuously processed, each bus master basically issues a bus request at a cycle below the request cycle 302. Also,
The one-time data transfer amount 303 is the amount of data that each bus master needs to transfer in the corresponding request cycle 302.

In the example shown in the figure, when it is necessary to continuously transfer data, the bus master A must transfer 1000 kilobytes (KB) of data every 2000 microseconds (μs). B is 10
This indicates that 100 KB of data must be transferred every 00 μs, and the bus master C must transfer 400 KB of data every 4000 μs.

That is, the bus master A is a bus master that needs to maintain the transfer rate of 500 KB / ms in the range of 2000 us, and the bus master B is 10
The bus master C is a bus master that needs to transfer at a transfer rate of 100 KB / ms in the range of 00 us, and the bus master C is 100 KB / m in the range of 4000 us.
The transfer rate information 300 in the figure indicates that the bus master needs to transfer data at a transfer rate of s. Of the bus masters A to C, the bus master B has the smallest time margin for securing the transfer rate, and the bus master C has the largest time margin for securing the transfer rate.

The external device having a CPU or the like may determine the transfer rate information 300 according to the specifications of each bus master and input the transfer rate information 300 to the memory control unit 110. In this way, the control content of the memory control unit 110 is set. The memory control unit 110 is general-purpose because the determined transfer rate information 300 can be externally input. Figure 3
FIG. 4 is a diagram showing a data structure and an example of contents of timing information generated by the timing information generation unit 112 and stored in the timing information storage unit 113.

As shown in the figure, timing information 400
Is composed of a request detection cycle 401 and an intra-cycle bus use permission time 402 for each bus master. Here, the request detection cycle 401 is information indicating a time determined by the timing information generation unit 112 as an interval at which the arbitration unit 114 detects a bus request from the bus masters A to C.

The intra-cycle bus use permission time 402 is
This is information indicating the time at which each bus master should be permitted to use the memory bus, that is, the time at which the bus use right should be granted so that each bus master can transfer necessary data in the request detection period 401. . The bus bandwidth of the memory bus of the unified memory 200 is assumed to be 800 KB / ms.

Each time in the timing information is
Actually, for example, it is represented by the count number of the clock signal generated by the clock generator 190. <Operation> Hereinafter, the memory control unit 110 having the above-described configuration
The operation of will be described. In the state where the transfer rate information storage unit 111 stores the transfer rate information transmitted from the external device, the timing information generation unit 112 operates as shown in FIG.
Perform the operation shown in.

FIG. 4 is a flow chart showing the operation of the timing information generator 112. The timing information generation unit 112 refers to the request cycle for each bus master included in the transfer rate information, and determines the shortest request cycle as the request detection cycle in the timing information (step S11). Subsequently, the timing information generation unit 112 uses the transfer rate information and the request detection period determined in step S11 to obtain the data transfer amount per request detection period for each bus master (step S12), and the obtained data. By dividing the transfer amount by the bus bandwidth of the memory bus, the in-cycle bus use permission time in the timing information is obtained (step S13). The timing information generation unit 112 stores the bus bandwidth of the memory bus in a memory or the like inside the LSI, and uses it to perform the calculation in step S13.

The timing information thus obtained is
It is stored in the timing information storage unit 113 by the timing information generation unit 112. It is assumed that such an operation of the timing information generation unit 112 is performed within a short period of time, for example, after the current is supplied to the LSI. Note that, for example, the transfer rate information 30 having the content illustrated in FIG.
The timing information generated by the timing information generation unit 112 based on 0 has the content illustrated in FIG.

Next, after the timing information is generated,
The arbitration process performed by the arbitration unit 114 will be described. Figure 5
6 is a flowchart showing an arbitration process performed by the arbitration unit 114. Based on the timing information and the clock signal supplied from the clock generator 190 at regular intervals, the arbitration unit 114 waits for the time to arrive at each request detection cycle (hereinafter referred to as “request detection timing”) and then detects the request. It is checked at each timing whether or not a bus request is issued from each bus master (step S21).

The arbitration unit 114 determines whether or not a bus request from any of the bus masters has been detected during the inspection in step S21 (step S22),
If no bus request is detected from any of the bus masters, the process returns to step S21 and waits for the next request detection timing. When it is determined in step S22 that the bus request has been detected, the arbitration unit 114 sets 1 of the bus master issuing the bus request.
Then, the bus use right is given (step S23).

The arbitration unit 114, after granting a bus mastership to a certain bus master, waits for the in-cycle bus mastership permission time for that bus master to elapse by counting the clock signal, and at the time of elapse, the bus mastership The application is stopped (step S24). That is, steps S23 and S
By 24, the GNT signal line to a certain bus master is activated only for the in-cycle bus use permission time and then inactivated.

After step S24, the arbitration unit 114 determines whether or not a bus request from a bus master different from the bus master that has already been granted the bus use right has been detected at the time of the immediately preceding inspection at step S21. (Step S25), if not detected, Step S25
The process returns to step 21 and waits for the arrival of the next request detection timing.

When it is determined in step S25 that a bus request from a bus master different from the bus master to which the bus use right has already been given has been detected after the inspection, the arbitration unit 114 returns to the process of step S23. Therefore, if the passage of time is expressed as the continuation of the request detection cycle, the arbitration unit 114, in each request detection cycle, gives each bus master that has issued a bus request before that cycle, the amount of the bus use permission time within the corresponding cycle. You will only be given the right to use the bus.

FIG. 6 is a timing chart showing a temporal change between the bus request from the bus masters A to C and the grant of the bus use right by the memory control unit 110. This shows the result of the memory control unit 110 arbitrating the contention of the memory access by each bus master based on the transfer rate information 300 illustrated in FIG. As is clear from the figure, the request detection cycle is 1000 μs in total for the bus master B having the shortest bus request cycle, and the bus masters A, B, and C that have issued the bus request are sequentially arranged in each request detection cycle. 625 μs,
The bus use right is given to each of 125 μs and 125 μs. Since the bus bandwidth of the memory bus is 800 KB / ms, the bus master A is 500 KB, the bus master B is 100 KB, and the bus master C is within the request detection period.
Is transferring 100 KB of data.

Therefore, the bus master A transfers 1000 KB of data in 2000 ms, and the bus master B transfers the data.
Performs data transfer of 100 KB in 1000 ms, the bus master C transfers data of 400 KB in 4000 ms, and each bus master can ensure the required transfer rate with the required accuracy and perform the data transfer. <Second Embodiment> A memory control unit according to the second embodiment of the present invention will be described below. The memory control unit 110 described in the first embodiment has a function of arbitrating the contention of the memory access between the bus masters A to C that needs to transfer data with the memory at a constant transfer rate. However, the memory control unit according to the second embodiment does not need to maintain a constant transfer rate, and the bus master A including the bus master D that transfers data to and from the memory irregularly is added.
It has a function of arbitrating the memory access contention between D to D.

<Structure> FIG. 7 is a block diagram of an LSI 500 including a memory control unit according to the second embodiment of the present invention.
Note that FIG. 7 shows the unified memory 200 in addition to the LSI 500. The LSI 500 includes a memory control unit 510, a bus master A121, a bus master B122, a bus master C123, a bus master D124, and a clock generator 190, and is connected to the unified memory 200. Although not shown in FIG. 7, the LSI 50
0 is also connected to other external devices.

Note that among the constituent elements of the LSI 500, those basically the same as the constituent elements of the LSI 100 shown in the first embodiment are denoted by the same reference numerals in FIG. 7 as in FIG. The description is omitted. here,
The clock generator 190 is a circuit that supplies a clock signal to the memory control unit 510, the bus masters A to D, and the unified memory 200.

The bus master D124 is the bus masters A to C.
Independently of this, the unified memory 200 is accessed and data is transferred. That is, the bus master D issues a bus request to the memory control unit 510 when data transfer is necessary, obtains the bus use right from the memory control unit 510, and while the bus use right is obtained, the clock generator 190 is obtained. Data is transferred in synchronization with the arbitration unit 514 of the memory control unit 510 at a timing based on the clock signal from

The bus master D124 is different from the bus masters A to C of the type that needs to transfer data at a constant transfer rate, that is, the type that periodically issues bus requests (hereinafter referred to as "periodic type"). , A type that issues a bus request irregularly (hereinafter, "irregular type"
Say. ) Is a bus master, and is, for example, an MPU or the like that receives an interrupt from the outside and performs processing in response to an input from a user of a device on which the LSI is mounted.

In FIG. 7, the bus requests from the bus masters are REQ-A, REQ-B and REQ, respectively.
-C and REQ-D are used to give the bus use right to each bus master, GNT-A, GNT-B, and GNT-, respectively.
It is represented by C and GNT-D. In addition, the memory control unit 51
0 arbitrates access to the unified memory 200 of the bus masters A to D based on the transfer rate information transmitted from the external device, and includes a transfer rate information storage unit 111, a timing information generation unit 112, and timing information storage. It has a unit 113, an arbitration unit 514, and an irregular master information storage unit 515.

The irregular master information storage unit 515 is a memory area in which irregular master information indicating irregular bus masters is stored in advance. The irregular master information is arbitration unit 51.
4 is information necessary for recognizing which of the irregular bus masters. The arbitration unit 514 refers to the irregular master information stored in the irregular master information storage unit 515 and the timing information stored in the timing information storage unit 113, and based on the clock signal from the clock generator 190, a predetermined value. At a timing, a bus master other than the aperiodic type bus master, that is, the presence / absence of a bus request from the regular type bus masters A to C is inspected, and the bus master issuing the bus request is sequentially and selectively granted the right to use the bus request. Bus master A within the detection cycle
When there is time left to grant the bus use right to none of C to C, the bus use right is given to the irregular bus master as long as a bus request is issued from the irregular bus master.

<Operation> The operation of the memory control unit 510 having the above configuration will be described below. The timing information generation unit 112 performs the same operation as the operation described in the first embodiment (see FIG. 4). FIG. 8 is a flowchart showing the arbitration process performed by the arbitration unit 514.

The arbitration unit 514 waits for the request detection timing to arrive on the basis of the timing information and the clock signal supplied from the clock generator 190 at regular intervals, and at the request detection timing, other than the irregular bus master. It is checked whether or not a bus request is issued from each bus master, that is, each regular bus master (step S31).

The arbitration unit 514 determines whether or not a bus request from any of the regular type bus masters has been detected during the inspection in step S31 (step S32). When it is determined in step S32 that the bus request has been detected, the arbitration unit 514 grants the bus use right to one of the regular type bus masters that has issued the bus request (step S33) and counts the clock signal. By doing so, it waits for the in-cycle bus use permission time for the bus master to elapse, and when the time elapses, the grant of the bus use right is stopped (step S34). That is,
Through steps S33 and S34, the GNT signal line to one fixed-duration bus master is activated for the in-cycle bus use permission time and then inactivated.

After the step S34, the arbitration unit 514 determines whether or not a bus request from a regular type bus master different from the bus master which has already been granted the bus use right is detected after the inspection in the immediately preceding step S31. Is determined (step S35). If it is determined in step S35 that the bus request from the regular type bus master different from the bus master that has already been granted the bus use right after the inspection has been detected in the inspection in step S31, the arbitration unit 514 returns to the processing in step S33, and In the case of, the arbitration unit 514 determines whether or not the next request detection timing has arrived (step S36), and when it determines that the next request detection timing has arrived, performs the processing of step S31. .

If no bus request is detected from any of the bus masters in step S32, the arbitration unit 514 skips the processes of steps S33 to S35 and performs the determination process of step S36. If it is determined in step S36 that the next request detection timing has not arrived, the arbitration unit 514
Checks whether or not a bus request is issued from the irregular bus master (step S37), and if a bus request is detected, grants the bus right to the irregular bus master (step S37). S38), when the bus request from the irregular bus master is stopped or when the next request detection timing arrives, the bus right is not granted (step S39), and the process returns to the determination process of step S36.

Even if no bus request from the irregular bus master is detected in step S37, the arbitration unit 514 returns to the determination processing in step S36. Therefore, if the passage of time is expressed as the continuation of the request detection cycle, the arbitration unit 514 uses the in-cycle bus for each regular type bus master that has issued a bus request before that cycle in each request detection cycle. The bus use right is given only for the permitted time, and if a bus request is issued from the irregular bus master in the remaining time in the cycle, the bus use right is given to the irregular bus master.

FIG. 9 is a timing chart showing a temporal change between the bus request from the bus masters A to D and the grant of the bus use right by the memory control unit 510. As shown in the figure, in each request detection cycle, the arbitration unit 514 issues a bus request from the aperiodic type bus master D for the remainder of the time when the regular type bus masters A to C are granted the bus use right. Then, the bus master D is granted the bus use right.

When the bus master D to which the bus use right is granted within the request detection period starting from a certain request detection timing arrives at the next request detection timing without stopping the issuance of the bus request within the request detection period. Then, the grant of the bus use right to the bus master D is stopped. Also, if there is a bus that does not issue a bus request at the request detection timing among the regular bus masters, the time during which the bus usage right can be granted to the irregular bus master within the request detection period become longer.

<Modified Example of Arbitration Processing> An example in which the above-described arbitration processing by the arbitration unit 514 is modified so that the bus mastership of an irregular bus master is granted earlier will be described. FIG. 10 is a flowchart showing a modified example of the arbitration process performed by the arbitration unit 514.

First, the arbitration unit 514 checks whether or not a bus request is issued from each bus master of the regular type bus master when the request detection timing arrives, and checks all the bus masters for which the bus request has been detected. Calculate the total bus permission time within the cycle of
The time obtained by subtracting the total from the request detection cycle is set as the surplus time (step S51). Here, the surplus time means a time during which the bus use right can be given to a certain irregular bus master within the request detection period.

Subsequently, the arbitration unit 514 determines whether or not a bus request from any of the regular type bus masters has been detected during the inspection in step S31 (step S52). If it is determined in step S52 that the bus request has been detected, the arbitration unit 51
4 grants the bus use right to one of the regular type bus masters that has issued the bus request (step S53), and counts the clock signal so that the in-cycle bus use permission time for the bus master elapses. wait,
When the time elapses, the grant of the bus use right is canceled (step S5).
4). That is, in steps S53 and S54, the GNT signal line to one fixed-duration bus master is activated for the in-cycle bus use permission time and then inactivated.

When it is determined in step S52 that the bus request has not been detected, the arbitration unit 514 skips the processes of steps S53 and S54 and performs the determination process of step S55. Step S54
After that, the arbitration unit 514 determines whether or not the next request detection timing has arrived (step S55), and if it has arrived, returns to the processing of step S51, and if it has not arrived, checks whether the surplus time is 0 or not. Judgment (step S5
6).

In step S56, when the arbitration unit 514 determines that the surplus time is not 0, that is, when the surplus time is present, the arbitration unit 514 checks whether a bus request is issued from the irregular bus master. (Step S
57) When a bus request is detected, the bus mastership is granted to the irregular bus master, and the surplus time is counted down in accordance with the elapsed time of the bus mastership (step S58). When the bus request from the irregular bus master is cancelled, or when the surplus time becomes zero, the grant of the bus use right is canceled (step S59), and the process returns to the determination process of step S56.

The surplus time determined in step S51 is counted down by the time when the bus right is given to the irregular bus master in step S58. However, the countdown of the surplus time is stopped when the surplus time becomes zero. If it is determined in step S56 that the surplus time is 0, or if a bus request from an irregular bus master is detected in step S57, the arbitration unit 514 determines that the regular type other than the bus master to which the bus use right has already been granted. It is determined whether or not the bus request from the bus master has been detected in step S51 (step S60). If not detected, the process returns to step S55, and if detected, the process returns to step S53.

Further, in step S55, the arbitration unit 51
When it is determined that the next request detection timing has come, 4 returns to the process of step S51 for inspecting the bus request from each regular type bus master at the next request detection timing. With such a modified arbitration process, the arbitration unit 514 causes the regular-type bus master, which is transferring data at the time when the irregular-type bus master issues a bus request, to use the bus for the in-cycle bus use permission time. As soon as the right is granted, the bus mastership is given to the irregular bus master, so that the irregular bus master can start data transfer promptly when data transfer is necessary. That is, the arbitration unit can suppress the access latency for the memory access by the irregular bus master by performing the modified arbitration process.

FIG. 11 is a timing chart showing a temporal change between the bus request from the bus masters A to D and the grant of the bus use right by the memory control unit 510 when the arbitration process performed by the arbitration unit 514 is modified. . As shown in the figure, the arbitration unit 514 is a regular bus master A.
When a bus request is issued from an irregular bus master D while granting the bus use right to the bus master D, the bus use right is given to the bus master D next to the bus master A, and then to the fixed type bus masters B and C. Sequential bus usage rights are granted, and the regular bus masters A and B are sequentially granted bus usage rights in the next request detection cycle. While the bus master B is granted the bus usage right, the irregular bus master D When a bus request is issued, the bus master B is followed by the bus master D.
To the regular-type bus master C, and then to the regular bus master C. <Supplement> Although the memory control device according to the present invention has been described above based on the first and second embodiments, it is needless to say that the present invention is not limited to these embodiments. That is, (1) The number of bus masters shown in both embodiments may be any number as long as it is plural. However, for all of the regular type bus masters, transfer rate information indicating the transfer rate and the time interval within which the transfer rate should be maintained is set to L.
When there is an irregular bus master that needs to be input to SI, irregular master information for specifying all irregular bus masters is irregular master information storage unit 51.
Must be stored in 5.

A plurality of unified memories may be connected to the LSI, and in this case, the memory control unit, for each unified memory, has the unified memory as described in the first or second embodiment. It is only necessary to arbitrate access conflicts between all bus masters that access the. (2) The memory control unit 110 shown in the first embodiment and the memory control unit 510 shown in the second embodiment may all be constructed as a hardware circuit, or may be composed of an MPU and a memory. It may be constructed so that the MPU executes the program to realize the arbitration function. (3) In both of the embodiments, the transfer rate information is the information including the request period for each bus master and the data transfer amount of one time, but the transfer rate information guarantees the transfer rate and the transfer rate. Any combination of information may be used as long as the information indicates the minimum time interval to be used. (4) Although the transfer rate information shown in both embodiments is input from an external device, an initial value may be stored in advance.

The transfer rate information can be input at any time, and every time the transfer rate information is input, the timing information generating section 112 generates timing information based on the transfer rate information and the timing information storing section. 11
3 may be stored. Since the arbitration unit 114 and the arbitration unit 514 determine the time for granting the bus use right to each bus master based on the timing information, dynamic arbitration control can be realized.

In the second embodiment, the bus masters are classified into the regular type and the non-periodic type, but this is the classification depending on whether or not the data transfer for which the guarantee of the transfer rate is required is performed.
Depending on the content of transfer rate information input to the LSI from the outside, even the same bus master may be of a regular type or an irregular type. (5) The bus bandwidth of the memory bus referred to by the timing information generation unit 112 shown in both embodiments is LS.
It may be possible to input from the outside of I. (6) The memory control unit 110 shown in the first embodiment and the memory control unit 510 shown in the second embodiment transmit information for specifying the request detection timing such as the request detection period to each bus master, In response to this, each bus master may issue a bus request at the request detection timing. (7) In both embodiments, the grant of the bus use right to the bus master is realized by activating the GNT signal line, and the suspension of the grant of the bus use right is realized by inactivating the GNT signal line. However, the present invention is not limited to these implementation methods, and may be implemented by any method as long as it is a method that can notify the bus master of permission or prohibition of bus use.

For example, the bus mastership is notified to the bus master by instantaneously activating a certain signal line, and the suspension of the bus mastership is instantaneously activated by another signal line. May be notified. Further, although the regular type bus master described in the embodiment keeps the REQ signal line active as long as data transfer is necessary, the method of issuing a bus request is not limited to this. For example, the memory control unit 110 and the memory control unit 510 may notify each bus master of the amount of data that can be transferred within the request detection period based on the transfer rate information, and each bus master will notify the notified data. The REQ signal line may be activated momentarily when the amount of transmission is required. (8) Unified memory 200 shown in both embodiments
Is not limited to a memory having a particular memory architecture and can be any memory.

Further, the memory bus connecting between the bus master and the unified memory shown in both embodiments is composed of a common signal line even if it is composed of separate signal lines of an address bus and a data bus. It may be done.
In the case of the common signal line, address information and data are transmitted in a time division manner between the bus master and the unified memory. Further, the bus between the bus master and the unified memory may be connected via the interface unit in the memory control unit, and the interface unit may perform processing such as address decoding. (9) In the LSI described in each embodiment, it is basically assumed that each bus master accesses memory areas independent of each other in one unified memory, but each bus master is duplicated. It does not matter even if the memory area is accessed. (10) In the second embodiment, the timing information generator 11
2 is the request detection cycle which is the shortest request cycle among the request cycles of the regular bus masters indicated in the transfer rate information, and the bus usage right to each regular bus master issuing a bus request at each request detection cycle. Although it was decided to grant, the request detection cycle is
It may be less than or equal to the shortest request cycle of the regular bus master.

For example, half of the shortest request cycle of the regular bus master may be set as the request detection cycle. When the request detection cycle is shortened, the bus is used after receiving the bus request from the irregular bus master. The time required to grant the right can be shortened. It should be noted that it is possible to input from outside the LSI information indicating what proportion of time is the request detection period for the shortest request period of the regular bus master, and based on that information, The request detection cycle may be determined.

[0074]

As described above, the memory control device according to the present invention selectively grants the right to use the memory bus to any of a plurality of bus masters sharing the memory, thereby competing for access to the memory. A memory control device that arbitrates, and for each of a plurality of bus masters, a transfer rate when the bus master transfers data to and from the memory, and a time period that determines a range in which the transfer should be guaranteed at the transfer rate. Holding means for holding transfer rate information indicating an interval, unit time calculating means for defining a time equal to or shorter than the smallest one of the time intervals corresponding to each bus master as a unit time, and each bus master,
Bus usage permission time calculating means for obtaining a bus usage permission time which is the time required for V transfer based on the bus bandwidth of the memory bus when the amount of data that can be transferred in the unit time according to the corresponding transfer rate is V; In each of a plurality of unit time zones obtained by periodically dividing the passage of time by the unit time, a right-of-use grant means for granting a right of use of the memory bus to each bus master for a corresponding bus-use permission time. It is characterized by being provided.

Further, the memory control device according to the present invention is
A memory control device that arbitrates access competition to a memory by selectively granting a right to use a memory bus to a plurality of bus masters that access mutually independent memory areas in one memory. A holding unit that holds transfer rate information indicating a transfer rate when the bus master transfers data to and from the memory and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate. A unit time calculating means for setting a time equal to or smaller than the smallest one of the time intervals corresponding to each bus master as a unit time, and for each bus master, V is a data amount that can be transferred in the unit time according to a corresponding transfer rate. Based on the bus bandwidth of the memory bus, the time required for V transfer is the bus license. In each of a plurality of unit time zones obtained by periodically dividing the elapsed time into the unit time, the bus use permission time calculating unit for obtaining the time, and for each bus master, the bus use permission time corresponding to the corresponding bus use permission time And a usage right granting means for granting a usage right.

As a result, even if the conditions concerning the transfer rates required by the respective bus masters are not unified, the transfer rates are adjusted so that the conditions concerning the transfer rates of the bus masters with the minimum transfer waiting margin can be satisfied. Therefore, it becomes possible for each bus master to perform data transfer while keeping the transfer rate constant with the required time accuracy.

Further, by using this memory control device, even when it is necessary to change the condition regarding the transfer rate of each bus master, the stored transfer rate information is simply rewritten to meet the request of each bus master. It becomes possible for each bus master to transfer data to and from the memory at the transfer rate. From this, it can be said that this memory control device can be utilized even if the bus master that is the target of access conflict control is replaced.

Here, the memory control device includes a detection means for detecting a bus request from each bus master,
The usage right granting unit may grant the usage right in the unit time zone to each bus master whose bus request is detected by the detecting unit before the start of each unit time slot. . As a result, the bus master sharing the memory can perform the data transfer while maintaining the required transfer rate by acquiring the bus right when issuing the bus request when there is data to be transferred. As a result, the circuit configuration of the memory control device is simpler than that when a bus request is detected within a certain unit time, and the bus master that issued the bus request is granted the bus use right within that unit time. Can be anything.

The bus master can be classified into a regular bus master that requires a constant transfer rate when transferring data to and from a memory, and other irregular bus masters. Holds the transfer rate information for each of a plurality of fixed type bus masters, the bus use permission time calculating means obtains the bus use permission time for each fixed type bus master, and the use right granting means In each unit time zone, each regular bus master whose bus request is detected before the start of the unit time zone is given a right to use the memory bus for the corresponding bus use permission time, and the bus means is detected by the detecting means. The sum of the bus use permission time corresponding to each regular type bus master where the request is detected is subtracted from the unit time. The Rino time may be granted irregular type bus use right of the memory bus to the bus master as the upper limit.

As a result, even when the regular bus master that needs to transfer data at a constant transfer rate and the other irregular bus master share the memory, the regular bus master needs the necessary time accuracy. With this, it becomes possible to perform data while keeping the transfer rate constant. Further, the usage right granting means is operable to detect the bus request from the irregular bus master during the unit time period while the detecting means grants the bus usage right to the regular bus master. The bus usage right may be granted to the irregular bus master as soon as the bus usage right is granted to the regular bus master.

As a result, the irregular bus master can quickly perform data transfer after the need for data transfer occurs. Further, the holding unit may acquire and hold the transfer rate information from outside the memory control device. As a result, even when it is necessary to change the transfer rate by changing the function of each bus master, it is possible to provide appropriate transfer rate information from the outside, and as a result, memory access contention between bus masters is properly arbitrated. Will be done.

Further, the holding means may hold the transfer rate information in an area rewritable by a device external to the memory control device. As a result, even when it is necessary to change the transfer rate of each bus master and the like, by rewriting the transfer rate information from outside as needed, contention of memory access between bus masters can be appropriately arbitrated.

Further, the memory control device is connected to the bus masters by signal lines for permitting bus use,
The usage right granting means may grant the bus usage right to the bus master for the bus usage permission time only by activating the signal line connected to the bus master for the bus usage permission time. This allows
It becomes possible to easily realize the granting of the bus use right whose time is limited by one signal line.

Further, the unit time calculating means may determine the time of the smallest one of the time intervals corresponding to each bus master as the unit time. As a result, the transfer rate of each bus master can be adjusted relatively easily by using the bus master having the minimum transfer waiting margin as a reference. Further, the LSI according to the present invention is a memory control that arbitrates access competition to a memory by selectively granting a right to use a memory bus to a plurality of circuits that share a memory. An LSI including a device, wherein each of the circuits is
The memory control device is a circuit that requires data to be transferred at a constant transfer rate to and from a memory, and the memory control device relates to the transfer rate when the circuit transfers data to and from the memory, and A holding unit that holds transfer rate information indicating a time interval that defines a range in which transfer should be guaranteed at a transfer rate, and a unit time that is equal to or less than the smallest of the time intervals corresponding to each circuit. For the unit time calculation method and each circuit defined as
Bus usage permission time calculating means for obtaining a bus usage permission time which is a time required for the transfer of V based on the bus bandwidth of the memory bus when the amount of data that can be transferred in the unit time according to the corresponding transfer rate is V; In each of a plurality of unit time zones obtained by periodically dividing the passage of time by the unit time, a usage right granting unit that grants a right to use the memory bus to each circuit for a corresponding bus usage permission time. It is characterized by being provided.

As a result, each of the plurality of internal circuits of the LSI can perform data transfer with the memory shared by the LSIs while maintaining the required transfer rate with the required time accuracy.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an LSI 100 including a memory control unit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a data configuration and an example of contents of transfer rate information transmitted from an external device and stored in a transfer rate information storage unit 111.

FIG. 3 is a diagram showing a data configuration and an example of contents of timing information generated by a timing information generation unit 112 and stored in a timing information storage unit 113.

FIG. 4 is a flowchart showing an operation of the timing information generation unit 112.

5 is a flowchart showing an arbitration process performed by an arbitration unit 114. FIG.

6 is a timing chart showing a temporal change between a bus request from the bus masters A to C and a grant of the bus use right by the memory control unit 110. FIG.

FIG. 7 is a configuration diagram of an LSI 500 including a memory control unit according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing an arbitration process performed by an arbitration unit 514.

9 is a timing chart showing a temporal change between a bus request from the bus masters A to D and a bus usage right granted by the memory control unit 510. FIG.

FIG. 10 is a flowchart showing a modified example of the arbitration process performed by the arbitration unit 514.

FIG. 11 shows a bus request from the bus masters A to D,
9 is a timing chart showing a temporal change with the grant of the bus use right by the memory control unit 510 when the arbitration processing performed by the arbitration unit 514 is modified.

[Explanation of symbols]

100,500 LSI 110, 510 memory control unit 111 Transfer rate information storage unit 112 Timing Information Generation Unit 113 Timing information storage section 114, 514 Mediation section 121-124 Bus Master 190 clock generator 200 Unified memory 515 Irregular master information storage unit

Claims (19)

[Claims] 1. A memory controller for arbitrating access competition to a memory by selectively granting a right to use a memory bus to any one of a plurality of bus masters sharing a memory, and for each of the plurality of bus masters. Holding means for holding transfer rate information indicating a transfer rate when the bus master transfers data to and from the memory and a time interval defining a range in which the transfer should be guaranteed to be performed at the transfer rate, When a unit time calculating means that determines a time less than or equal to the smallest one of the time intervals corresponding to each bus master as a unit time and V is a data amount that can be transferred in the unit time according to a corresponding transfer rate for each bus master, Based on the bus bandwidth of the memory bus, the bus use permission time, which is the time required to transfer V, is calculated. In each of a plurality of unit time zones that are obtained by calculating the bus use permission time and periodically dividing the elapsed time by the unit time, each bus master is given the right to use the memory bus for the corresponding bus use permission time. A memory control device, comprising: a usage right granting means for granting. 2. The memory control device includes detection means for detecting a bus request from each bus master, and the usage right granting means detects the bus request before the start of each unit time zone by the detection means. 2. The memory control device according to claim 1, wherein the usage right is given to each of the bus masters that have been executed in the unit time zone. 3. The bus master can be classified into a regular bus master that needs to maintain a constant transfer rate when transferring data to and from a memory, and other irregular bus masters, and the holding means. Is for holding the transfer rate information for each of a plurality of fixed type bus masters, the bus use permission time calculating means obtains the bus use permission time for each fixed type bus master, and the use right granting means is In each unit time zone, each regular bus master whose bus request was detected before the start of the unit time zone is given a right to use the memory bus for the corresponding bus use permission time, and the bus means is detected by the detection means. Remaining amount obtained by subtracting the sum of the bus use permission time corresponding to each regular type bus master where the request is detected from the unit time. 3. The memory control apparatus according to claim 2, wherein the bus mastership of the memory bus is given to the irregular bus master with an upper limit of a predetermined time. 4. The usage right granting means detects a bus request from an irregular bus master while granting the bus usage right to the regular bus master by the detecting means in each of the unit time zones. 4. The memory control device according to claim 3, wherein the non-periodic type bus master is granted the bus use right as soon as the grant of the bus use right to the regular type bus master is completed. 5. The memory control device according to claim 4, wherein the holding unit acquires and holds the transfer rate information from outside the memory control device. 6. The holding means stores the transfer rate information,
5. The memory control device according to claim 4, wherein the memory control device is held in a rewritable area by a device external to the memory control device. 7. The memory control device is connected to the bus masters via signal lines for permitting bus use, and the use right granting means grants a bus use right to a bus master for a bus use permission time only. 5. The memory control device according to claim 4, wherein the signal line connected to the bus master is activated for a bus use permission time. 8. The memory control device according to claim 1, wherein the unit time calculation means determines a time of the smallest one of the time intervals corresponding to each bus master as a unit time. 9. The memory control device according to claim 1, wherein the holding means acquires and holds the transfer rate information from outside the memory control device. 10. A memory control device for arbitrating access competition to a memory by selectively granting a right to use a memory bus to a plurality of bus masters that access mutually independent memory areas in one memory. Transfer rate information indicating, for each of the plurality of bus masters, a transfer rate when the bus master transfers data to and from the memory and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate. Holding unit for holding the unit, unit time calculating unit for setting a time equal to or smaller than the smallest one of the time intervals corresponding to each bus master as a unit time, and data for each bus master that can be transferred in the unit time at a corresponding transfer rate. When it is necessary to transfer V based on the bus bandwidth of the memory bus when the amount is V The bus usage permission time calculating means for obtaining the bus usage permission time and the corresponding bus usage for each bus master in each of a plurality of unit time zones obtained by periodically dividing the elapsed time by the unit time. A memory control device comprising: a usage right granting means for granting a usage right of a memory bus only for a permission time. 11. The memory control device comprises detection means for detecting a bus request from each bus master, and the usage right grant means detects the bus request before the start of each unit time zone by the detection means. 11. The memory control device according to claim 10, wherein the usage right is given to each of the bus masters that have been processed in the unit time zone. 12. The bus master can be classified into a regular bus master that requires a constant transfer rate when transferring data to and from a memory, and other irregular bus masters, and the holding means. Is for holding the transfer rate information for each of a plurality of fixed type bus masters, the bus use permission time calculating means obtains the bus use permission time for each fixed type bus master, and the use right granting means is In each unit time zone, each regular bus master whose bus request was detected before the start of the unit time zone is given a right to use the memory bus for the corresponding bus use permission time, and the bus means is detected by the detection means. The sum of the bus use permission time corresponding to each regular type bus master where the request is detected is subtracted from the unit time. 12. The memory control device according to claim 11, wherein the bus mastership of the memory bus is given to the irregular bus master with the remaining time as an upper limit. 13. The usage right granting means detects a bus request from an irregular bus master while granting the bus usage right to the regular bus master by the detecting means in each of the unit time zones. 13. The memory control device according to claim 12, wherein the bus usage right is granted to the irregular bus master as soon as the bus usage right is granted to the regular bus master. 14. A plurality of circuits that share a memory, and a memory control device that arbitrates access competition to a memory by selectively granting a right to use a memory bus to any one of the plurality of circuits. In the LSI, each of the circuits is a circuit that needs to transfer data to and from the memory at a constant transfer rate, and the memory control device includes: Holding means for holding transfer rate information indicating a transfer rate at the time of transferring data and a time interval defining a range in which the transfer should be guaranteed at the transfer rate, and the time interval corresponding to each circuit. A unit time calculating means that determines the time less than the smallest one as the unit time, and the amount of data that can be transferred in the unit time according to the corresponding transfer rate for each circuit When V is set, the bus use permission time calculating means for obtaining the bus use permission time which is the time required for V transfer based on the bus bandwidth of the memory bus, and the time lapse are periodically obtained by dividing the time by the unit time. In each of the plurality of unit time zones, the LS is provided with a usage right granting unit that grants a usage right of the memory bus to each circuit for a corresponding bus usage permission time.
I. 15. The LSI according to claim 14, wherein each of the circuits is a circuit that transfers data between memory areas independent of each other in the memory. 16. The memory control device includes detection means for detecting a bus request from each of the circuits, and the usage right granting means causes the detection means to detect a bus request before the start of each unit time zone. 15. The LS according to claim 14, wherein the usage right is given to each of the detected circuits in the unit time zone.
I. 17. The circuit can be classified into a regular bus master that requires a constant transfer rate when transferring data to and from a memory, and other irregular bus masters. Is for holding the transfer rate information for each of a plurality of fixed type bus masters, the bus use permission time calculating means obtains the bus use permission time for each fixed type bus master, and the use right granting means is In each unit time zone, each regular bus master whose bus request was detected before the start of the unit time zone is given a right to use the memory bus for the corresponding bus use permission time, and the bus means is detected by the detection means. The sum of the bus use permission time corresponding to each regular type bus master where the request is detected is subtracted from the unit time and the remaining 17. The LSI according to claim 16, wherein the bus mastership of the memory bus is given to the irregular bus master with a time limit as an upper limit. 18. The usage right granting means detects a bus request from an irregular bus master while granting the bus usage right to the regular bus master by the detecting means in each of the unit time zones. 18. The LSI according to claim 17, wherein the non-periodic bus master is granted the bus usage right as soon as the grant of the bus usage right to the regular bus master is completed. 19. The LSI according to claim 14, wherein the holding unit acquires and holds the transfer rate information from outside the LSI.