JP2002229932A - Dma transfer device and data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA transfer device of a cycle steal system in which such a useless CPU cycle, for the constant monitoring of the transfer termination of DMA, that is caused by the transfer of bus use rights to the CPU, does not occur, and to provide a data transfer system including these DMA transfer devices. SOLUTION: The DMA transfer device 2 has a bus request generation circuit 14, a DMA transfer termination flag reference counter 11 that is a counter for counting the number of times of reference to termination flag that is a detection means for detecting the status of waiting for DMA transfer termination of a CPU 3, an upper bound of the number of times of reference management register 12 of a register that makes the setting of the upper bound of the number of times of reference, and a comparator 13 that compares the discrete value of the DMA transfer termination flag reference counter 11 with the set value of the number of times of reference management register 12. If the number of times of reference, for the termination status, to the DMA transfer device 2 that is detected with the detection means hits a fixed number of times or more, it is judged that the CPU has entered the status of monitoring the termination of DMA transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer device and a data transfer system.

[0002]

2. Description of the Related Art As a method of transferring data from a device to a memory or from a memory to a device without a CPU, there is a direct memory access (hereinafter, referred to as DMA) transfer method. The DMA transfer method includes an interlock method and a cycle steal method.

In the case of the interlock method, once the DMA transfer device acquires the right to use the bus, it does not release the bus until the transfer end condition of the DMA transfer device is satisfied.
DMA transfer is performed continuously.

In the case of the cycle stealing method, the DMA transfer device releases the bus each time transfer of one transfer unit such as a predetermined time or a predetermined number of times is completed, and transfers the right to use the bus to the CPU. Thereafter, when a transfer request of the DMA transfer device is generated again, the DMA transfer device acquires the right to use the bus from the CPU, performs DMA transfer in one transfer unit again,
After the transfer is completed, the right to use the bus is transferred to the CPU again. This operation is repeatedly executed until the transfer end condition of the DMA transfer is satisfied.

[0005] The interlock system is easy to control, and D
High throughput is obtained as MA transfer. But,
During DMA transfer, CPU operation cannot be intervened.
For example, even in a situation where quick processing of the CPU is required, such as an interrupt response, there arises a problem that the response must wait for the end of the DMA transfer.

[0006] In the cycle steel method, C
Since the PU can acquire the right to use the bus, there is no problem that the necessary CPU operation is limited as in the interlock method. However, hardware resources for realizing the cycle stealing method and a bus arbiter for bus arbitration are required. In addition, arbitration frequently occurs to acquire the right to use the bus based on the arbitration system of the bus arbiter. Therefore, there is a problem that the transfer speed for completing the transfer of the desired data is reduced.

The current DMA transfer system is generally a cycle steal system, and the interlock system tends to be limited to a case where a user is consciously setting and using the system. That is, the interlock method is the cycle steal type DM
The elements that are additional functions in the A transfer device are strong.

Next, the configuration of a data transfer system including a conventional DMA transfer device will be described with reference to FIG. FIG.
1 is a configuration diagram of a data transfer system including a conventional DMA transfer device. The data transfer system 51 includes a DMA transfer device 52, a CPU 53, and a bus arbiter.
54. DMA transfer device 52 and CPU
53 is connected to the address bus 55 and the data bus 56, respectively. The bus arbiter 54 and the DMA
The transfer device 52 has a bus request line 7
1 and a bus grant line 72. Further, the bus arbiter 54 and the CPU 53
Are connected by a bus request line 73 and a bus grant line 74.

The DMA transfer device 52 includes a bus request generation circuit 64, and can set a fixed interlock system, a fixed cycle steal system, or both. The DMA transfer device 52 issues a bus use request (bus request) from the bus request generation circuit 64 to the bus arbiter 54. The bus arbiter 54 has a CPU according to a bus arbitration unit (not shown).
The right to use the address bus 55 and the data bus 56 is given to the DMA transfer device 53 and the DMA transfer device 52. In FIG. 2, the CPU 53 and the DMA transfer device 52 serve as bus masters. However, there are systems having a configuration using a plurality of bus masters.

In a data transfer system adopting the DMA transfer system, for the purpose of efficient use of the bus, for example, Japanese Patent Application Laid-Open No. Hei 11-232215 discloses a method of transmitting information on a bus use state by utilizing an idle time of the bus. A technique relating to a bus controller, a bus master device, and a control method of a bus control system in which each bus master schedules a use request based on the bus controller is disclosed. Japanese Patent Application Laid-Open No. Hei 5-282243 discloses that when a command such as a multiplication instruction is processed for a plurality of cycles inside the CPU and a bus is not used for a predetermined period of time, a command of the CPU is decoded. A technique relating to a bus master device for giving a right to use a bus to a DMA transfer device and an electronic apparatus using the device are disclosed.

[0011]

In a data transfer system employing a cycle stealing type DMA transfer device for the purpose of increasing the bus use efficiency, when the CPU is in a state of waiting for the end of the DMA transfer, the following process is performed. There is such a problem. That is, when the right to use the bus is delegated to the CPU, the useless C such as always monitoring the end of the DMA transfer is monitored.
A PU cycle occurs. Therefore, this CPU
The cycle reduces the transfer speed of the DMA transfer. On the other hand, if the interlock method is adopted to increase the transfer speed of the DMA transfer device, there is a problem that CPU cycles that require a quick response such as an interrupt response are limited. No measures against these problems are described in the above prior art.

Therefore, the present invention has been made to solve the above-mentioned problem, and its purpose is to wastefully monitor the end of DMA transfer by transferring the right to use the bus to the CPU. Cycle steal type DMA transfer device without occurrence of CPU cycle, and DMA having both cycle steal type and interlock type
It is an object to provide a transfer device and a data transfer system including these DMA transfer devices.

[0013]

The present invention has the following arrangement as means for solving the above-mentioned problems.

(1) A DMA transfer apparatus for performing DMA transfer of data at predetermined time intervals or at predetermined times, wherein a CPU detects that the DMA transfer apparatus is in a state of waiting for transfer completion and outputs a predetermined signal. It is characterized by comprising detecting means, and bus request generating means for outputting a bus use request in response to an output signal of the detecting means.

In this configuration, the DMA transfer device has a C
Detecting means for detecting that the PU is in a transfer end waiting state of the DMA transfer device and outputting a predetermined signal; and bus request generating means for outputting a bus use request in response to an output signal of the detecting means. , The DMA transfer of data is performed at an arbitrary time or at an arbitrary number of times as necessary. Therefore,
Since the DMA transfer device detects by the detection means that the CPU is waiting for the transfer completion of the DMA transfer device, the CPU always monitors the end of the DMA transfer of the cycle steal type DMA transfer device in the conventional CPU. The occurrence of CPU cycles can be reduced, and the transfer speed of the DMA transfer device can be increased.

(2) In the above configuration, a transfer number setting means capable of changing one data transfer time or the number of data transfers in the transfer end waiting state is provided.

In this configuration, the DMA transfer device can change one data transfer time or the number of data transfers in the transfer end waiting state by the transfer number setting means. Therefore, the DMA transfer device can occupy the right to use the bus for a required time or a required number of times.

(3) The detection means outputs a predetermined signal to the bus request generation means when the end status reference count of the CPU is equal to or more than a predetermined count or the reference cycle is equal to or less than a predetermined cycle. Features.

In this configuration, when the end status reference count of the CPU is equal to or greater than a predetermined count or the reference cycle is equal to or less than a predetermined cycle, the detection means of the DMA transfer device outputs a predetermined signal to the bus request generation means. I do. Therefore, there is no need for the CPU to constantly monitor the end of the DMA transfer by the DMA transfer device.

(4) In the configuration of (3), the detecting means sets an end flag reference number counting means for counting the number of times the CPU refers to the end flag, and sets an upper limit of the end flag reference number of the CPU. Reference count upper limit registration means,
The count value of the end flag reference count counting means is compared with the set value of the reference count upper limit registration means. If the count value of the end flag reference count counting means exceeds the set value of the reference count upper limit registration means, a predetermined value is determined. And comparison means for outputting the signal of

In this configuration, the comparing means of the detecting means includes the number of times the end flag reference number counting means has referred to the CPU end flag and the upper limit of the CPU end flag reference number set in the reference number upper limit registering means. Settings and
And outputs a predetermined signal when the count value of the end flag reference count counting means exceeds the set value of the reference count upper limit registration means. Therefore, when the CPU
The transfer end waiting state can be easily detected with a simple configuration.

(5) The DMA transfer according to any one of claims 1 to 3, wherein upon detecting occurrence of an interrupt, the bus request generation means outputs a signal for transferring the right to use the bus to the CPU. apparatus.

In this configuration, when the occurrence of an interrupt is detected, the bus request generating means outputs a signal for transferring the right to use the bus to the CPU. Therefore, when an interrupt occurs, the interrupt processing can be performed promptly.

(6) D according to any one of claims 1 to 4
CP for transmitting and receiving data via MA bus and bus
U and a bus use right arbitration device for arbitrating a bus use request of the DMA transfer device and the CPU.

In this configuration, the data transfer system includes: a DMA transfer device according to any one of claims 1 to 4; a CPU for transmitting and receiving data via a bus;
A bus use right arbitration device for arbitrating a bus use request of the CPU. Therefore, it is possible to easily reduce unnecessary CPU cycles such as always monitoring the end of DMA transfer in a data transfer system including a cycle steal type DMA transfer device without any significant increase in circuit scale. , The transfer speed of the DMA transfer device can be increased.

(7) When the detected interrupt occurrence factor is not the end interrupt of the DMA transfer device, the bus arbitration device reassigns the right to use the bus to the DMA transfer device after the end of the interrupt response. Features.

In this configuration, the bus arbitration device of the data transfer system, if the detected interrupt occurrence factor is not the end interrupt of the DMA transfer device, after the end of the interrupt response, transfers the bus use right to the DMA transfer device again. Give. Therefore, when an interrupt is detected, DM
If the transfer process of the A transfer device has not been completed,
After the interrupt response, the DMA transfer device can quickly return to a state in which the bus can be occupied for a necessary time or number of times.

(8) An interrupt controller for detecting an interrupt signal is provided, and instead of the DMA transfer device,
The interrupt controller has the detection unit, and the detection unit determines that the number of times the target bit of the DMA transfer device of the interrupt controller detects the end of transfer interruption detection is equal to or more than a predetermined number of times, or the reference cycle is equal to or less than a predetermined cycle. Then, a predetermined signal is output to the bus request generating means.

In this configuration, in the data transfer system, instead of the DMA transfer device, an interrupt controller for detecting an interrupt signal detects that the CPU is in a transfer end wait state of the DMA transfer device and outputs a predetermined signal. The detection means outputs the target bit of the transfer end interrupt detection in the DMA transfer device of the interrupt controller is a predetermined number of times or more,
Alternatively, when the reference cycle becomes equal to or shorter than a predetermined cycle, a predetermined signal is output to the bus request generation unit. Therefore, the mounting position of the detection means is changed according to the characteristics of the data transfer system, and the CPU is controlled by the interrupt controller.
Is in a state of waiting for the transfer completion of the DMA transfer device.

(9) An address decoder for decoding an address referred to by the CPU is provided. Instead of the DMA transfer device, the address decoder has the detecting means. When the reference count is equal to or more than a predetermined number or when the reference cycle is equal to or less than a predetermined cycle, a predetermined signal is output to the bus request generating means.

In this configuration, in the data transfer system, instead of the DMA transfer device, an address decoder for decoding an address referred to by the CPU includes
Detecting means for detecting that the transfer device is in a transfer end waiting state and outputting a predetermined signal;
The number of references to a specific address of the PU is equal to or more than a predetermined number,
Alternatively, when the reference cycle becomes equal to or shorter than a predetermined cycle, a predetermined signal is output to the bus request generation unit. Therefore, the mounting position of the detecting means is changed according to the state of the data transfer system, and the address decoder causes the CPU to operate as D.
It is possible to detect that the MA transfer device is in a transfer end waiting state.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a data transfer system according to an embodiment of the present invention will be described with reference to FIG. Figure 1
1 is a schematic configuration diagram of a data transfer system. The data transfer system 1 includes a DMA transfer device 2, a CPU 3, and a bus arbiter 4 serving as a bus arbitration device.
It is a configuration including. The DMA transfer device 2 and the CPU 3
They are connected to an address bus 5 and a data bus 6, respectively. Further, the bus arbiter 4 and the DMA transfer device 2
It is connected by a bus request line 21 and a bus grant line 22. Further, the bus arbiter 4 and the CPU 3 are connected to a bus request line 23 and a bus grant.
It is connected by a line 24.

The DMA transfer device 2 can set a cycle steal system or both a cycle steal system and an interlock system, and has a bus request generating circuit 14 as a bus request generating means. Also, DM
A DMA end flag reference counter 1 which is a counter that counts the number of times the end flag has been referred to as a detecting means for detecting the DMA transfer end wait state of the CPU 3 in the A transfer apparatus 2
1. A reference count upper limit management register 12 that is a register for setting an upper limit of the reference count, and a comparator 13 that compares the count value of the DMA end flag reference counter 11 with the set value of the reference count upper limit register 12. .

In the data transfer system of the present invention, the DMA
If the number of times the transfer status of the transfer device 2 is referred to exceeds a certain value, it is determined that the CPU 3 is monitoring the end of the DMA transfer. That is, the DMA end flag reference counter 11 counts up each time the CPU 3 refers to the DMA end flag which is the end status, and when the CPU 3 exceeds the value of the reference count upper limit management register 12 set in advance, the CPU 3 sets the DMA transfer device 2 (Hereinafter referred to as a DMA transfer end wait state).

In this DMA transfer end wait state, D
In the MA transfer device 2, the DMA end flag reference counter 1
Reference count upper limit management register 1 in which the count value of 1 is set in advance
When the value exceeds 2, a predetermined signal is output from the comparator 13. This signal is input to the bus request generation circuit 14. The bus request generation circuit 14 has a function of continuously issuing a bus request. In this case, the bus request generation circuit 14 outputs the bus request to the bus arbiter 4 via the bus request line 21.

Upon receiving a bus request from the CPU 3 and the DMA transfer device 2, the bus arbiter 4 arbitrates the right to use the bus, and gives one of the CPU 3 and the DMA transfer device 2 the right to use the address bus 5 and the data bus 6. give. At this time, by setting the priority of the bus use right of the DMA transfer device 2 higher than that of the CPU 3, the DMA transfer device 2 can occupy the bus use right in the DMA transfer end waiting state.

Further, a transfer number setting register 15 for setting one data transfer time or data transfer number (the number of transfers in one transfer unit) such as a predetermined time or a predetermined number of times in the DMA transfer end waiting state is provided. It is provided as. When the bus request generation circuit 14 outputs a bus request, the bus request generation circuit 14 refers to the number of transfers in one transfer unit set in the transfer number setting register 15. One data transfer time or the number of data transfers (the number of transfers in one transfer unit) can be set to an arbitrary value. This allows for more flexible arbitration of bus usage rights.

In the above configuration, the DMA transfer device is provided with a function of canceling a bus request every time the transfer of the transfer count setting register is completed. As a result, DM
In the DMA transfer end waiting state, the A transfer device 2 can occupy the right to use the bus for a necessary time or number of times.

In the data transfer system of the present invention,
When the reference cycle of the end status to the DMA transfer device becomes equal to or less than a predetermined cycle, it may be determined that the CPU is monitoring the end of the DMA transfer.

Next, a bus cycle of the data transfer system according to the embodiment of the present invention will be described. FIG. 3 is a timing chart of a bus cycle of the conventional data transfer system 51 shown in FIG. FIG. 4 is a timing chart of a bus cycle in the data transfer system 1 of the present invention shown in FIG.

In the conventional data transfer system 51, the right to use the bus is transferred from the DMA transfer device 52 to the CPU 53 at regular intervals. That is, as shown in FIG. 3, when the DMA transfer device 52 uses the bus for four cycles, the CPU 53 uses the bus for at least one cycle. In the data transfer system, this cycle is repeated until the data transfer ends.

On the other hand, in the data transfer system 1 of the present invention, the CPU 3 enters the DMA transfer end wait state by referring to the DMA end flag a predetermined number of times. As shown in FIG. 4, when the CPU 3 detects the DMA transfer end waiting state when using the bus for at least one cycle, the
The A transfer device 2 can then occupy the bus for any period based on its configuration or settings.

The bus request generation circuit 14 of the DMA transfer device 2 shown in FIG.
A configuration is also conceivable in which a detection signal at the time of occurrence of an interrupt is input. The DMA transfer device 2 detects a DMA transfer end wait state, and detects that an interrupt has been detected while the DMA transfer device is holding the right to use the bus.
When a quick response is required, the DMA transfer device 2 outputs to the bus arbiter a signal for canceling the bus request by itself or lowering the priority of the bus request than the CPU 3. As a result, the DMA transfer device 2 can immediately transfer the right to use the bus to the CPU 3 after the necessary transfer processing is completed.

FIG. 5 is a bus timing chart of the data transfer system when an interrupt is detected.
In FIG. 5, the DMA transfer device 2 detects a DMA transfer end wait state, and thereafter occupies the bus and performs data transfer. Then, an interrupt is detected, and the interrupt detection signal is sent to the bus request generation circuit 1 of the DMA transfer device 2.
When the number is input to 4, the right to use the bus is immediately transferred to the CPU after necessary transfer processing is completed. Thereby, the CP
U3 can immediately execute an interrupt response.

If the interrupt factor at the time of detecting the interrupt is not the generation of the end interrupt of the DMA transfer device 2, the DMA transfer device 2 can occupy the bus for a necessary time or number of times after the interrupt response. Can be quickly returned to. Therefore, when the interrupt input changes to the inactive side, the bus request generation circuit 14 keeps issuing the bus request again for the necessary time or number of times.

When the DMA transfer completion state is detected and the DMA transfer apparatus 2 holds the right to use the bus, the right to use the bus is transferred to the CPU 3 because an interrupt is detected. Alternatively, the end flag reference counter 11 may be cleared. As a result, after the interrupt response, the data transfer system 1 returns to the state of executing the normal cycle stealing transfer method. When the DMA transfer completion waiting state is detected again, the DMA transfer device 2 can preferentially use the right to use the bus.

The above components need not be in the DMA transfer device. The mounting position can be changed as needed. For example, the data transfer system 1 has a configuration in which an interrupt controller (not shown) includes a DMA end flag reference counter 11, a reference count upper limit management register 12, and a comparator 13, which are detection means for detecting a DMA transfer end wait state. Is also good. In this case, the reference number upper limit management register 12 stores the interrupt controller D
The upper limit value or the lower limit value of the reference cycle is set for the target bit of the end interrupt detection at the time of transfer of the MA transfer device 2. The DMA end flag reference counter 11
Is to check the number of times of reference or the reference cycle of the target bit for detecting the occurrence of the transfer end interrupt in the DMA transfer device of the interrupt controller. Then, the DMA end flag reference counter 11 reads the D of the interrupt controller.
The comparator 13 outputs a predetermined signal to the bus request generation circuit 14 when the number of times of reference to the target bit for detecting the end interrupt of the transfer in the MA transfer device is equal to or more than a predetermined number or the reference cycle is equal to or less than a predetermined cycle. To do. Thereby, according to the characteristics of the data transfer system,
By changing the mounting position of the detecting means, the interrupt controller can detect that the CPU is in the transfer end waiting state of the DMA transfer device.

In the data transfer system 1, D
DMA which is a detecting means for detecting a state of waiting for the end of MA transfer
An end flag reference counter 11, a reference count upper limit management register 12, and a comparator 13 may be provided in an address decoder (not shown). In this case, the upper limit value or the lower limit value of the number of times of reference of the target bit for the detection of the end interrupt occurrence detection at the time of the transfer by the DMA transfer device 2 of the reference address decoder to the specific address of the CPU 3 is set in the reference number upper limit management register 12. . The DMA end flag reference counter 11 checks the number of times the CPU 3 refers to a specific address or the reference cycle. When the number of references to a specific address from the CPU 3 is equal to or more than a predetermined number or the reference cycle is equal to or less than a predetermined cycle, the comparator 13 sends a predetermined signal to the bus request generation circuit 14. Output to This makes it possible for the address decoder to detect that the CPU is in a state of waiting for the transfer completion of the DMA transfer device, by changing the mounting position of the detection means according to the characteristics of the data transfer system. According to the above configuration method, when the data transfer system 1 is waiting for an interrupt to occur, there is a case where the register of the interrupt controller is not accessed until the interrupt occurs.
It is particularly effective in such a case.

It should be noted that the specific address is an address indicating the position of a hardware resource constituting a data transfer system used for constantly monitoring the end of the transfer of the DMA transfer device 2. Any address may be used as long as it is necessary to monitor the completion of the transfer by the DMA transfer device 2.

[0050]

According to the present invention, the following effects can be obtained.

(1) The DMA transfer device includes: a detection unit for detecting that the CPU is in a transfer completion waiting state of the DMA transfer device and outputting a predetermined signal; and a bus use request in response to the output signal of the detection unit. And a bus request generating means for outputting a DMA request.
It is possible to reduce the occurrence of useless CPU cycles such as constantly monitoring the end of transfer, and increase the transfer speed of the DMA transfer device.

(2) The DMA transfer device can also add transfer number setting means, which can change one data transfer time or the number of data transfers in the transfer waiting state by the transfer number setting means. It is possible to occupy the right to use the bus for a short time or a necessary number of times.

(3) When the end status reference count of the CPU is equal to or greater than a predetermined count or the reference cycle is equal to or less than a predetermined cycle, the detection means of the DMA transfer device outputs a predetermined signal to the bus request generation means. Therefore, the CPU need not always monitor the end of the DMA transfer of the DMA transfer device.

(4) It is also conceivable that the bus request generation means outputs a signal for transferring the right to use the bus to the CPU when the occurrence of an interrupt is detected. In this case, when an interrupt occurs, the interrupt processing is immediately performed. It can be performed.

(5) A data transfer system comprising: a DMA transfer device according to any one of claims 1 to 4; a CPU for transmitting and receiving data via a bus; and a DMA transfer device and a bus used by the CPU. And a bus arbitration device for arbitrating requests. In a data transfer system including a cycle steal type DMA transfer device as a component without any significant increase in the circuit size, particularly,
It is possible to reduce the occurrence of useless CPU cycles such as constantly monitoring the end of the transfer of the MA, and it is possible to increase the transfer speed of the DMA transfer device.

(6) The bus arbiter of the data transfer system, if the detected interrupt occurrence factor is not the end interrupt of the DMA transfer device, gives the bus transfer right to the DMA transfer device again after responding to the interrupt. Therefore, if the transfer processing of the DMA transfer device is not completed when the interrupt is detected, the DMA transfer device immediately returns to a state where the bus can be occupied for a necessary time or number of times after the interrupt response. Can be.

(7) In the data transfer system, instead of the DMA transfer device, an interrupt controller for detecting an interrupt signal detects that the CPU is in a transfer completion waiting state of the DMA transfer device and outputs a predetermined signal. A detecting means for outputting a signal, wherein the detecting means comprises a DMA of an interrupt controller.
A predetermined signal is output to the bus request generating means when the number of times of reference to the target bit for detecting the occurrence of the transfer end interrupt in the transfer device is equal to or more than a predetermined number or the reference cycle is equal to or less than a predetermined cycle. As described above, changing the mounting position of the detecting means according to the characteristics of the data transfer system,
The interrupt controller can detect that the CPU is in a state of waiting for the transfer completion of the DMA transfer device.

(8) In the data transfer system, in place of the DMA transfer device, an address decoder for decoding an address referred to by the CPU detects a state that the CPU is waiting for the DMA transfer device to complete the transfer and outputs a predetermined signal. When the number of references to a specific address of the CPU is equal to or more than a predetermined number or the reference cycle is equal to or less than a predetermined cycle, the detection means outputs a predetermined signal to the bus request generation means. Output. As described above, the mounting position of the detecting means is changed according to the characteristics of the data transfer system, and the address decoder can detect that the CPU is in the transfer end waiting state of the DMA transfer device.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a data transfer system.

FIG. 2 is a configuration diagram of a data transfer system including a conventional DMA transfer device.

FIG. 3 is a timing chart of a bus cycle of the conventional data transfer system 51 shown in FIG.

FIG. 4 is a timing chart of a bus cycle in the data transfer system 1 of the present invention shown in FIG.

FIG. 5 is a bus timing chart of the data transfer system when an interrupt is detected.

[Explanation of symbols]

 1,51-data transfer system 2,52-DMA transfer device 3,53-CPU 11-DMA end flag reference counter 12-reference upper limit management register 13-comparator 14,64-bus request generation circuit

Claims (8)

[Claims] 1. A DMA transfer device for performing DMA transfer of data at predetermined time intervals or at predetermined counts, wherein a CPU detects that the DMA transfer device is in a transfer end waiting state and outputs a predetermined signal. And a bus request generating means for outputting a bus use request in response to an output signal of the detecting means. 2. The DMA transfer device according to claim 1, further comprising a transfer number setting unit that can change one data transfer time or the number of data transfers in the transfer end waiting state. 3. The detection means outputs a predetermined signal to the bus request generation means when the end status reference count of the CPU is equal to or more than a predetermined count or when a reference cycle is equal to or less than a predetermined cycle. Claim 1.
Or the DMA transfer device according to 2. 4. The DMA transfer device according to claim 1, wherein said bus request generation means outputs a signal for delegating a right to use a bus to a CPU upon detecting occurrence of an interrupt. . 5. The DM according to claim 1, wherein
A transfer device and CPU for transmitting and receiving data via bus
A data transfer system comprising: a DMA transfer device; and a bus use right arbitration device that arbitrates a bus use request of the CPU. 6. The bus use right arbitration device, if the detected interrupt occurrence factor is not an end interrupt of the DMA transfer device, gives the right to use the bus to the DMA transfer device again after the end of the interrupt response. Claim 5
A data transfer system according to claim 1. 7. An interrupt controller for detecting an interrupt signal, wherein the interrupt controller has the detecting means instead of the DMA transfer device, wherein the detecting means detects a transfer of the interrupt controller in the DMA transfer device. 7. The method according to claim 5, wherein a predetermined signal is output to the bus request generation means when the number of times of reference to the target bit for the detection of the end interrupt occurrence is equal to or more than a predetermined number or when the reference cycle is equal to or less than a predetermined cycle.
A data transfer system according to claim 1. 8. An address decoder for decoding an address referred to by a CPU, wherein the address decoder has the detecting means in place of the DMA transfer device, and the detecting means detects a specific address of the CPU. 7. The data transfer system according to claim 5, wherein when the number of times of reference is equal to or more than a predetermined number or when the number of times of reference is equal to or less than a predetermined number, a predetermined signal is output to the bus request generation unit.