JP3497478B2 - DMA transfer device and data transfer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer device and a data transfer system.

[0002]

2. Description of the Related Art As a method of transferring data from a device to a memory or from a memory to a device without passing through a CPU, there is a direct memory access (hereinafter referred to as DMA) transfer method. The DMA transfer system includes an interlock system and a cycle steal system.

In the interlock system, once the DMA transfer device acquires the right to use the bus, it does not release the bus until the transfer end condition of the DMA transfer device is satisfied.
DMA transfer is continuously performed.

In the case of the cycle steal method, the DMA transfer device releases the bus each time a transfer of one transfer unit such as a predetermined time or a predetermined number of times is completed, and transfers the bus use right to the CPU. After that, when another transfer request of the DMA transfer device is generated, the DMA transfer device acquires the right to use the bus from the CPU and performs the DMA transfer of one transfer unit again,
After the transfer is completed, the bus usage right is transferred to the CPU again. This operation is repeatedly executed until the transfer end condition of the DMA transfer is satisfied.

The interlock system is easy to control, and D
High throughput can be obtained as MA transfer. But,
During the DMA transfer, CPU operation cannot be performed, so
For example, even in a situation where the CPU needs to perform a quick process such as an interrupt response, there arises a problem that the response must wait for the end of the DMA transfer.

In the cycle steal system, C at regular intervals
Since the PU can acquire the right to use the bus, the problem that the necessary CPU operation is limited unlike the interlock system does not occur. However, a hardware resource for realizing the cycle steal method and a bus arbiter for bus arbitration are required. Further, arbitration frequently occurs in order to acquire the right to use the bus based on the arbitration method of the bus arbiter. Therefore, there arises a problem that the transfer speed for completing the transfer of desired data becomes slow.

The current DMA transfer method is generally the cycle steal method, and the interlock method tends to be limited to the case where the user consciously sets and uses it. In other words, the interlock system is the cycle steal system DM
A transfer device has many additional functions.

Next, the structure of a data transfer system including a conventional DMA transfer device will be described with reference to FIG. Figure 2
FIG. 1 is a configuration diagram of a data transfer system including a conventional DMA transfer device. The data transfer system 51 includes a DMA transfer device 52, a CPU 53, and a bus arbiter.
This is a configuration including 54. DMA transfer device 52 and CPU
53 is connected to the address bus 55 and the data bus 56, respectively. Also, the bus arbiter 54 and the DMA
The transfer device 52 uses the bus request line 7
1 and a bus grant line 72. Furthermore, the bus arbiter 54 and the CPU 53
Are connected by a bus request line 73 and a bus grant line 74.

The DMA transfer device 52 is provided with a bus request generation circuit 64, and it is possible to set the interlock system fixed, the cycle steal system fixed, or both types. The DMA transfer device 52 issues a bus use request (bus request) from the bus request generation circuit 64 to the bus arbiter 54. The bus arbiter 54 is a CPU according to a bus arbitration unit (not shown).
The use right of the address bus 55 and the data bus 56 is given to the 53 and the DMA transfer device 52. In FIG. 2, the CPU 53 and the DMA transfer device 52 are bus masters, but there is a system having a configuration using a plurality of bus masters.

In a data transfer system adopting a DMA transfer method, for the purpose of efficient use of the bus, for example, Japanese Patent Laid-Open No. 11-232215 discloses transmission of bus use status information by utilizing free time of the bus. , A technology relating to a bus controller, a bus master device, and a control method of a bus control system, in which each bus master schedules a usage request based on the above, are disclosed. Further, in Japanese Unexamined Patent Publication No. 5-282243, when the instruction of the CPU is deciphered and a bus, such as a multiplication instruction, which is processed for a plurality of cycles inside the CPU, is not used for a predetermined period when the bus is not used. , A technique relating to a bus master device for giving a right to use a bus to a DMA transfer device and an electronic device using the device are disclosed.

[0011]

In a data transfer system that employs a cycle stealing DMA transfer device for the purpose of improving bus utilization efficiency, when the CPU is waiting for the end of the DMA transfer, There is such a problem. That is, when the right to use the bus is transferred to the CPU, the end of the DMA transfer is constantly monitored, which is a wasteful C.
A PU cycle will occur. Therefore, this CPU
The cycle reduces the transfer rate of the DMA transfer. On the other hand, if the interlock system is adopted in order to increase the transfer rate of the DMA transfer device, there is a problem that CPU cycles that require a quick response such as an interrupt response are limited. No countermeasure for these problems is described in the above-mentioned prior art.

Therefore, the present invention was created in order to solve the above problem, and its purpose is to constantly monitor the end of DMA transfer by delegating the right to use the bus to the CPU. Cycle steal system DMA transfer device without generation of CPU cycle and DMA having both cycle steal system and interlock system
A transfer device and a data transfer system including these DMA transfer devices are provided.

[0013]

The present invention has the following structure as means for solving the above problems.

(1) A DMA transfer device for performing a DMA transfer of data at a predetermined time interval or a predetermined number of times, comprising a CPU
Bus There outputting a detection unit configured to detect and output a predetermined signal that is a transfer termination waiting state of DMA transfer device, bus use request according to a predetermined signal that said detecting means has <br/> Outputs And a request generation means.

In this configuration, the DMA transfer device is
A detecting means for outputting a predetermined signal by detecting that the CPU is transferred termination waiting state of the DMA transfer device, a bus request generating means for outputting a bus use request according to a predetermined signal that said detecting means has an output , Data DMA of
The transfer is performed at any time or every time as needed.
Therefore, the DMA transfer device is the detection means and the CPU is the DM.
Since it is detected that the transfer device A is in the transfer end waiting state, it is possible to reduce the occurrence of useless CPU cycles such as always monitoring the DMA transfer end of the cycle steal system DMA transfer device in the CPU as in the conventional case. , The transfer speed of the DMA transfer device can be increased.

(2) In the above configuration, a transfer number setting means capable of changing one data transfer time or the number of data transfers in the transfer end waiting state is provided.

In this configuration, the DMA transfer device can change the data transfer time or the number of data transfers once in the transfer end waiting state by the transfer number setting means. Therefore, the DMA transfer device can occupy the right to use the bus for the required time or the required number of times.

[0018] (3) the detection means, the exit status reference number of the CPU is higher than a predetermined number of times, or Referring cycle is below a predetermined cycle, to output the predetermined signal to the bus request generating means Is characterized by.

In this configuration, when the CPU end status reference frequency is equal to or greater than the predetermined frequency or the reference period is equal to or less than the predetermined period, the detection means of the DMA transfer device outputs a predetermined signal to the bus request generation means. To do. Therefore, the CPU does not have to constantly monitor the end of the DMA transfer of the DMA transfer device.

(4) In the configuration of (3), the detection means sets an end flag reference number counting means for counting the number of times the CPU has referred to the end flag, and an upper limit of the end flag reference number of the CPU. A reference count upper limit registration means,
The count value of the end flag reference number counting means and the set value of the reference number upper limit registering means are compared, and when the count value of the end flag reference number counting means exceeds the set value of the reference number upper limit registering means, a predetermined value is determined. And a comparing means for outputting the signal of.

In this structure, the comparing means of the detecting means refers to the number of times the end flag of the CPU is counted by the end flag reference number counting means and the upper limit of the reference number of the CPU end flag set in the reference number upper limit registering means. Setting value,
And a predetermined signal is output when the count value of the end flag reference number counting means exceeds the set value of the reference number upper limit registration means. Therefore, the CPU is the DMA of the DMA transfer device.
It is possible to easily detect that the transfer is in a waiting state with a simple configuration.

(5) The bus request generation means withdraws the bus use request when detecting the occurrence of an interrupt ,
Or lowering the priority of bus use requests
It

In this configuration, when the occurrence of an interrupt is detected, the bus use request is canceled or the bus use is stopped.
Lower the priority of the request . Therefore, when an interrupt occurs, it is possible to quickly perform the interrupt process.

(6) D according to any one of claims 1 to 4
CP for transmitting / receiving data to / from the MA transfer device via the bus
U and a bus use right arbitration device that arbitrates bus use requests of the DMA transfer device and the CPU.

In this configuration, the data transfer system includes a DMA transfer device according to any one of claims 1 to 4, a CPU for transmitting and receiving data via a bus,
A bus use right arbitration device that arbitrates the bus use request of the DMA transfer device and the CPU. Therefore, it is possible to easily reduce the occurrence of useless CPU cycles such as constantly monitoring the end of DMA transfer in a data transfer system including a DMA transfer device of a cycle steal system as a constituent element without any significant increase in the circuit scale. , The transfer speed of the DMA transfer device can be increased.

[0026]

[0027]

( 7 ) An interrupt controller for detecting an interrupt signal is provided, and instead of the DMA transfer device, the interrupt controller has the detecting means, and the detecting means is capable of checking the number of end statuses of the CPU. predetermined number of times or more, or when the reference period is equal to or less than a predetermined period, and outputs the predetermined signal to the bus request generating means.

In this configuration, in the data transfer system, instead of the DMA transfer device, an interrupt controller for detecting an interrupt signal detects that the CPU is in a transfer end waiting state of the DMA transfer device, and outputs a predetermined signal. It has a detecting means for outputting a detection means, the end of the CPU
When the number of times the status is referred to is greater than or equal to a predetermined number of times or the reference period is less than or equal to a predetermined period, a predetermined signal is output to the bus request generation means. Therefore, depending on the characteristics of the data transfer system, it is possible to change the mounting position of the detection means and detect by the interrupt controller that the CPU is waiting for the transfer end of the DMA transfer device.

[0030] (8) comprises an address decoder for decoding an address which the CPU refers, instead of the DMA transfer device, said address decoder having said sensing means, said sensing means, a specific address of said CPU reference number to the predetermined number of times or more, or when the reference period is equal to or less than a predetermined period, and outputs the predetermined signal to the bus request generating means.

In this structure, in the data transfer system, instead of the DMA transfer device, an address decoder for decoding an address referred to by the CPU is provided by the CPU by the DMA.
The transfer device has a detection unit for detecting that the transfer device is in a transfer end waiting state and outputting a predetermined signal, and the detection unit is the C
The number of times the PU refers to a specific address is a predetermined number of times or more,
Alternatively, when the reference cycle becomes equal to or shorter than the predetermined cycle, a predetermined signal is output to the bus request generation means. Therefore, according to the state of the data transfer system, the mounting position of the detecting means is changed and the CPU is controlled by the address decoder.
It is possible to detect that the MA transfer device is in a transfer end waiting state.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a data transfer system according to an embodiment of the present invention will be described with reference to FIG. Figure 1
FIG. 1 is a schematic configuration diagram of a data transfer system. The data transfer system 1 includes a DMA transfer device 2, a CPU 3, and a bus arbiter 4 which is a bus usage right arbitration device.
It is a configuration including. The DMA transfer device 2 and the CPU 3 are
It is connected to the address bus 5 and the data bus 6, respectively. In addition, the bus arbiter 4 and the DMA transfer device 2 are
It is connected by a bus request line 21 and a bus grant line 22. Further, the bus arbiter 4 and the CPU 3 have a bus request line 23 and a bus grant.
It is connected by the line 24.

The DMA transfer device 2 can set the cycle steal system or both the cycle steal system and the interlock system, and includes a bus request generation circuit 14 as a bus request generation means. Also, DM
The DMA end flag reference counter 1, which is a counter that counts the number of times the end flag is referred to, serves as a detection unit that detects the DMA transfer end wait state of the CPU 3 in the A transfer device 2.
1, a reference number upper limit management register 12 that is a register for setting the upper limit of the reference number, and a comparator 13 that compares the count value of the DMA end flag reference counter 11 with the set value of the reference number upper limit management register 12. .

In the data transfer system of the present invention, the DMA
When the number of times the end status is referred to the transfer device 2 exceeds a certain number of times, it is determined that the CPU 3 is in a state of monitoring the end of the DMA transfer. That is, the DMA end flag reference counter 11 counts up each time the CPU 3 refers to the DMA end flag, which is the end status, and when the preset count upper limit management register 12 value is exceeded, the CPU 3 causes the DMA transfer device 2 The transfer end waiting state (hereinafter referred to as the DMA transfer end waiting state) is entered.

In this wait state for completion of DMA transfer, D
In the MA transfer device 2, the DMA end flag reference counter 1
Reference count upper limit management register 1 with a count value of 1 set in advance
When the value exceeds 2, the comparator 13 outputs a predetermined signal. This signal is input to the bus request generation circuit 14. The bus request generation circuit 14 has a function of continuously issuing a bus request, and in this case, outputs the bus request to the bus arbiter 4 via the bus request line 21.

When the bus arbiter 4 receives a bus request from the CPU 3 and the DMA transfer device 2, the bus arbiter 4 arbitrates the right to use the bus, and either the CPU 3 or the DMA transfer device 2 acquires the right to use the address bus 5 and the data bus 6. give. At this time, by setting the priority of the bus use right of the DMA transfer device 2 higher than that of the CPU 3, the DMA transfer device 2 can occupy the bus use right in the waiting state of the DMA transfer end.

Further, the transfer number setting register 15 for setting one data transfer time or the number of data transfers (transfer number of one transfer unit) such as a predetermined time or a predetermined number of times in the DMA transfer end waiting state is provided in the transfer number setting means. It is set up as. Then, when the bus request generation circuit 14 outputs the bus request, the transfer number set in the transfer number setting register 15 is set to be referred to. The data transfer time or the number of times of data transfer (the number of transfers in one transfer unit) can be set to any value. This allows for more flexible bus usage arbitration.

Further, in the above configuration, the DMA transfer device is provided with the function of canceling the request of the bus each time the transfer of the transfer count setting register is completed. This allows DM
The A transfer device 2 can occupy the right to use the bus for the required time or number of times in the DMA transfer end waiting state.

In the data transfer system of the present invention,
When the reference cycle of the end status to the DMA transfer device is equal to or less than a certain cycle, it may be determined that the CPU is in the state of monitoring the end of the DMA transfer.

Next, the bus cycle of the data transfer system according to the embodiment of the present invention will be described. FIG. 3 is a timing chart of the bus cycle of the conventional data transfer system 51 shown in FIG. FIG. 4 is a timing chart of bus cycles in the data transfer system 1 of the present invention shown in FIG.

In the conventional data transfer system 51, the right to use the bus is transferred from the DMA transfer device 52 to the CPU 53 at regular intervals. That is, as shown in FIG. 3, when the DMA transfer device 52 uses the bus for 4 cycles, the CPU 53 uses the bus for at least 1 cycle. In the data transfer system, this cycle is repeated until the data transfer is completed.

On the other hand, in the data transfer system 1 of the present invention, the CPU 3 refers to the DMA end flag a predetermined number of times to enter the DMA transfer end wait state. As shown in FIG. 4, when the CPU 3 uses the bus for at least one cycle and detects a DMA transfer end waiting state, DM
The A transfer device 2 can then occupy the bus for any period of time based on its configuration or settings.

The bus request generation circuit 14 of the DMA transfer device 2 shown in FIG.
A configuration in which a detection signal when an interrupt occurs in is input is also conceivable. The DMA transfer device 2 detects the DMA transfer end wait state, and when the DMA transfer device holds the right to use the bus, the CPU detects that an interrupt is detected.
When a quick response is required, the DMA transfer device 2 outputs to the bus arbiter a signal for canceling the bus request by itself or lowering the priority of the bus request than the CPU 3. As a result, the DMA transfer device 2 can quickly transfer the bus use right to the CPU 3 after the necessary transfer processing is completed.

FIG. 5 is a bus timing chart of the data transfer system when an interrupt is detected.
In FIG. 5, the DMA transfer device 2 detects a DMA transfer end waiting state, and then occupies the bus to perform data transfer. Then, an interrupt is detected, and the interrupt detection signal is sent to the bus request generation circuit 1 of the DMA transfer device 2.
4 is input, the bus right of use is immediately transferred to the CPU after the necessary transfer processing is completed. This makes CP
U3 can immediately execute the interrupt response.

If the interrupt factor at the time of detecting the interrupt is not the end interrupt of the DMA transfer device 2, the DMA transfer device 2 can occupy the bus for the required time or number of times after the interrupt response. Can be quickly returned to. Therefore, when the interrupt input changes to the inactive side, the bus request generation circuit 14 continues to issue the bus request again for the required time or number of times.

Further, when the bus transfer right is transferred to the CPU 3 because an interrupt is detected or the like while the DMA transfer device 2 holds the bus use right by detecting the DMA transfer end waiting state. Alternatively, a configuration may be considered in which the end flag reference counter 11 is cleared. As a result, after the interrupt response, the data transfer system 1 returns to the state of executing the regular cycle steal transfer method. When the DMA transfer end waiting state is detected again, the DMA transfer device 2 can preferentially use the bus use right.

It should be noted that the above constituent elements do not have to be present in the DMA transfer device. The mounting position can be changed as required. For example, the data transfer system 1
In the above configuration, the interrupt controller (not shown) may include a DMA end flag reference counter 11, a reference number upper limit management register 12, and a comparator 13, which are detection means for detecting a DMA transfer end wait state. In this case, the reference count upper limit management register 12 subject bit reference number of end interrupt occurrence detection (end flag number of references to CPU 3)
Set the upper limit of or the lower limit of the reference cycle. Also, D
MA end flag reference counter 11, the end flag references exit target bit reference number of interrupts generated detection (CPU 3
Number of times) or the reference cycle. The end interrupt occurrence detection completion flag of the target bit reference number (CPU 3 of the DMA completion flag reference counter 11
When the reference number of times is equal to or greater than a predetermined number or the reference period is equal to or less than the predetermined period, the comparator 13 outputs a predetermined signal to the bus request generation circuit 14. Thereby, the mounting position of the detection means is changed according to the characteristics of the data transfer system, and the C
It is possible to detect that the PU is in the transfer end waiting state of the DMA transfer device.

In the data transfer system 1, D
DMA, which is a detection means for detecting the MA transfer end waiting state
The end flag reference counter 11, the reference count upper limit management register 12, and the comparator 13 may be provided in an address decoder (not shown). In this case, the reference number upper limit management register 12 is set with the upper limit value of the target bit reference number of the end interrupt occurrence detection at the time of transfer of the DMA transfer device 2 of the reference address decoder to the specific address of the CPU 3 or the lower limit value of the reference cycle. . Further, the DMA end flag reference counter 11 confirms the number of times the CPU 3 refers to a specific address or the reference cycle. Then, the DMA end flag reference counter 11 causes the comparator 13 to output a predetermined signal when the reference number from the CPU 3 to the specific address is equal to or larger than a predetermined number or the reference period is equal to or smaller than the predetermined period. To be output to. As a result, according to the characteristics of the data transfer system, it is possible to change the mounting position of the detecting means and detect by the address decoder that the CPU is in the transfer end waiting state of the DMA transfer device. In the above configuration method, when the data transfer system 1 is waiting for an interrupt, the register of the interrupt controller may not be accessed until the interrupt occurs.
It is particularly effective in such a case.

The specific address is an address indicating the position of a hardware resource constituting the data transfer system used for the purpose of constantly monitoring the end of transfer of the DMA transfer device 2. Any address may be used as long as it is necessary to monitor the end of transfer of the DMA transfer device 2.

[0050]

According to the present invention, the following effects can be obtained.

(1) In the DMA transfer device, the CPU is DMA
A detecting means for outputting a predetermined signal by detecting that a transfer end waiting state of the transfer device, where said detecting means has an output
Bus request generation means for outputting a bus use request in response to a constant signal, and with the above-mentioned configuration, the CPU always monitors the end of the DMA transfer of the cycle steal DMA transfer device in the conventional manner. CP
The occurrence of U cycles can be reduced and the transfer rate of the DMA transfer device can be increased.

(2) The DMA transfer device can be added with a transfer number setting means, and the transfer number setting means can change one data transfer time or the number of data transfers in the transfer waiting state. It becomes possible to occupy the right to use the bus for various times or as many times as necessary.

(3) When the CPU end status reference count is equal to or greater than a predetermined number or the reference period is equal to or less than a predetermined period, the detection means of the DMA transfer device outputs a predetermined signal to the bus request generation means. Therefore, the CPU does not have to constantly monitor the end of the DMA transfer of the DMA transfer device.

[0054] (4) When detecting the interrupt generation, the bus request generating means withdraw a bus request, or
A configuration in which the priority of the bus use request is lowered is also conceivable. In this case, when an interrupt occurs, the interrupt process can be performed promptly.

(5) A data transfer system, a DMA transfer device according to any one of claims 1 to 4, a CPU for transmitting and receiving data via a bus, and a bus use of the DMA transfer device and the CPU And a bus right arbitration device that arbitrates the request. Especially in a data transfer system having a cycle-stealing DMA transfer device as a constituent element without any significant increase in circuit scale,
It is possible to reduce the occurrence of useless CPU cycles such as constantly monitoring the end of transfer of MA, and it is possible to increase the transfer speed of the DMA transfer device.

[0056]

( 6 ) In the data transfer system, instead of the DMA transfer device, an interrupt controller for detecting an interrupt signal detects that the CPU is in a transfer completion waiting state of the DMA transfer device and sends a predetermined signal. The detecting means has a detecting means for outputting, and the detecting means outputs a predetermined signal to the bus request generating means when the number of times of reference of the end status of the CPU is equal to or more than a predetermined number of times or the reference period is less than a predetermined period. As described above, it is possible to detect that the CPU is in the transfer completion waiting state of the DMA transfer device by the interrupt controller by changing the mounting position of the detecting means according to the characteristics of the data transfer system.

( 7 ) In the data transfer system, instead of the DMA transfer device, an address decoder that decodes an address referred to by the CPU detects that the CPU is in a transfer end waiting state of the DMA transfer device, and outputs a predetermined signal. When the number of references to the specific address of the CPU is equal to or greater than a predetermined number or the reference cycle is equal to or less than a predetermined cycle, the detection means outputs a predetermined signal to the bus request generation means. Output. As described above, depending on the characteristics of the data transfer system, the mounting position of the detection means can be changed and the address decoder can detect that the CPU is in the transfer end waiting state of the DMA transfer device.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a data transfer system.

FIG. 2 is a configuration diagram of a data transfer system including a conventional DMA transfer device.

3 is a timing chart of a bus cycle of the conventional data transfer system 51 shown in FIG.

4 is a timing chart of a bus cycle in the data transfer system 1 of the present invention shown in FIG.

FIG. 5 is a bus timing chart of the data transfer system when an interrupt is detected.

[Explanation of symbols]

1,51-Data transfer system 2,52-DMA transfer device 3,53-CPU 11-DMA end flag reference counter 12-Reference count upper limit management register 13-comparator 14, 64-bus request generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-333949 (JP, A) JP-A-6-175966 (JP, A) JP-A-8-171529 (JP, A) JP-A-4- 306754 (JP, A) JP 5-151143 (JP, A) JP 9-305532 (JP, A) JP 2-181855 (JP, A) JP 64-78353 (JP, A) JP, 2000-293483 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/28 310 G06F 13/362 510

Claims (7)

(57) [Claims] 1. A DMA transfer device for performing a DMA transfer of data at a predetermined time interval or a predetermined number of times, wherein the CPU detects that the DMA transfer device is in a transfer end waiting state and outputs a predetermined signal. means and, DMA transfer device characterized by comprising a, a bus request generating means for outputting a bus use request according to a predetermined signal that said detecting means has outputted. 2. The DMA transfer apparatus according to claim 1, further comprising a transfer number setting means capable of changing a data transfer time or a data transfer number once in the transfer end waiting state. Wherein said detecting means, the exit status reference number of the CPU is higher than a predetermined number of times, or Referring cycle is below a predetermined cycle, to output the predetermined signal to the bus request generating means The DMA transfer device according to claim 1 or 2, wherein. 4. The bus request generation means cancels the bus use request when detecting the occurrence of an interrupt , and
4. The DMA transfer apparatus according to claim 1 , wherein the priority of the bus use request is lowered . 5. The DM according to any one of claims 1 to 4.
A transfer device and a CPU for transmitting and receiving data via a bus
And a bus usage right arbitration device that arbitrates bus usage requests of the DMA transfer device and the CPU. 6. An interrupt controller for detecting an interrupt signal, the interrupt controller having the detecting means instead of the DMA transfer device, and the detecting means, the detecting means referring to the end status of the CPU. 6. The data transfer system according to claim 5 , wherein the predetermined signal is output to the bus request generation means when the number of times is a predetermined number of times or more or the reference period is less than or equal to a predetermined period. 7. an address decoder for decoding an address which the CPU refers, instead of the DMA transfer device, said address decoder having said detection means, said detection means to a specific address of said CPU 6. The data transfer system according to claim 5 , wherein the predetermined signal is output to the bus request generation means when the number of times the reference is performed is a predetermined number of times or more or the reference period is a predetermined period or less.