JPH09190407A - Controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the dispersion of cyclic processing time in a device on which a multi-bus master function is mounted. SOLUTION: When a bus access processing is executed by a high frequency, a CPU unit 2 secures a system bus 4 till the series of processings are completed and releases a bus in accordance with the bus request of a peripheral unit when the bus access frequency is low. In the meantime, the peripheral unit 2 sets the uppermost value of transfer data quantity, divides the transfer data into plural cycles at every uppermost value so as to transfer it when it is judged that transfer data quantity is more than the uppermost value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device used, for example, in a PLC (programmable controller) or the like, and in particular, includes a CPU unit, a plurality of peripheral units that can be a bus master, and an arbiter circuit, and the CPU unit is cyclic. The present invention relates to a control device that performs processing.

[0002]

2. Description of the Related Art Conventionally, a control device having a multi-bus master configuration has, for example, as shown in FIG. 6, a plurality of peripheral units 1 each having a built-in microprocessor and capable of becoming a bus master, and buses from these peripheral units 1. There is an arbiter circuit 2 for controlling a request, and the peripheral unit 1 and the arbiter circuit 2 are connected by a single bus 10.

The control device having this multi-bus master structure performs the processing shown in FIG.

That is, a position as a certain bus master,
That is, when the peripheral unit 1 having the right to control the single bus 10 (hereinafter, simply referred to as a bus right) accesses a memory, an input / output device or the like (not shown), the bus 10 is used. A request to execute is output to the arbiter circuit 2 (step 710), and when the bus permission from the arbiter circuit 2 is confirmed (step 720), the memory, the input / output device or the like to be accessed is connected via the bus 1 ( After that, when the process for the memory, the input / output device, etc. is completed (step 730), the bus request is withdrawn to the arbiter circuit 2 (step 740) and the bus right is relinquished.

[0005]

However, among the control devices having such a multi-bus master configuration, the CP
The U unit regularly performs cyclic processing,
If the cyclic processing time is an important process, the arbiter circuit will not simply arbitrate the bus request,
There is a problem in that the cyclic processing time varies due to variations in the data transfer time and the like that are processed during the cyclic processing.

In particular, when there is a restriction that the cycle processing must be executed within a predetermined time, sometimes the processing cannot be performed within this restriction, which is a big problem.

In view of the above-mentioned problems, the present invention is based on C
It is an object of the present invention to provide a control device that reduces variations in cyclic processing time when a PU unit is performing cyclic processing.

[0008]

In order to achieve the above object, the invention according to claim 1 is provided with a CPU unit, a plurality of peripheral units that can be a bus master, and an arbiter circuit, and the CPU unit is cyclic. In the control device that performs processing, when the CPU unit performs bus access processing with high frequency, the bus right securing means that secures the bus until the series of processing is completed, and the peripheral unit, transfer data amount. Second upper limit value setting means for setting the upper limit value and second transfer value for determining whether the transfer data amount is larger than the upper limit value set by the second upper limit value setting means.
And the second data amount determining means determines that the transfer data amount is greater than or equal to the upper limit value set by the second upper limit value setting device, Each upper limit value is transferred in a plurality of cycles, and when it is determined that the transfer data amount is less than the upper limit value set by the second upper limit value setting means, this data is transferred as it is. And a second data transfer means.

According to a second aspect of the present invention, in the arbiter circuit according to the first aspect, when the CPU unit and the peripheral unit compete with each other when a bus use request occurs, the CPU unit acquires the bus right. It is characterized by doing so.

According to a third aspect of the present invention, in the first aspect of the invention, the arbiter circuit is connected to a position close to the CPU unit when the bus use requests from the peripheral units conflict. It is characterized in that the peripheral units that are present are allowed to acquire the bus right.

According to the present invention, when the CPU unit performs the bus access processing at high frequency, the bus is secured until the series of processing is completed, and the peripheral unit determines the transfer data amount. It is determined whether or not it is larger than the set upper limit value, and when it is determined that it is equal to or larger than the set upper limit value, this transfer data is
While transferring in a plurality of cycles, if it is determined that the value is less than the set upper limit value, this data is transferred as it is.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a control device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the control device of this embodiment.

The control device of this embodiment shows a construction of a building block type programmable controller (PLC), and includes a base unit 1, a CPU unit 2 for performing a predetermined cyclic processing, and a plurality of bus masters. The CPU unit 2 and each peripheral unit 3 are connected to each other via a system bus 4 such as a data bus.

The base unit 1 accommodates and mounts the CPU unit 2 and the peripheral unit 3 in a slot, and includes an arbiter circuit 11. The arbiter circuit 11 is a bus between the CPU unit 2 and the peripheral unit 3. It is configured to mediate rights.

The arbiter circuit 11 is designed so that when the CPU unit 2 and the peripheral unit 3 compete with each other when a bus use request occurs, the CPU unit 2 sets the acquisition of the bus right to a high level. Further, the arbiter circuit 11 sets the acquisition of the bus right to be higher for the peripheral unit 2 connected to the position closer to the CPU unit 2 when the bus use requests from the peripheral units 3 compete. ing.

The CPU unit 2 executes a predetermined cyclic process, and performs a control process such as a control process and an arithmetic process. An MPU 21, a bus I / F 22 which is an interface for transferring data to the system bus 4, and It is mainly composed of the shared memory 23.

Further, the CPU unit 2 is configured to continue to request the arbiter circuit 11 to use the bus until the series of processing is completed when the bus access processing is performed at high frequency.

The peripheral unit 3 is, for example, an I / O unit, and like the CPU unit 2, the MPU 31 for performing control processing such as control processing and arithmetic processing, and the bus I which is an interface for transferring data to the system bus 4. / F3
2 and the shared memory 33.

Further, like the CPU unit 2, when the transfer amount of transfer data exceeds a predetermined upper limit value, the peripheral unit 3 divides the transfer data into the upper limit values and divides the transfer data into a plurality of cycles. It is configured to transfer separately.

Now, the cycle processing performed by this PLC will be described.

The cyclic processing performed by this PLC includes
As shown in FIG. 2, the CPU unit 2 has a system bus 4
Has a low usage frequency (a) and a high usage frequency (b).

The period (a) in which the CPU unit 2 is infrequently used with respect to the system bus 4 is, for example, a period required for a hardware check inside the CPU unit 2, a period required for a tool service, a period required for an upper link service, and a CPU user. The time it takes to run the program has expired.

The system bus 4 of the CPU unit 2
During the period (b) in which the use frequency is high, the CPU unit 2 always reserves the bus right.

That is, the CPU unit 2 has a period (a)
While the bus right is always secured at the end of the period (b) and the bus right is released at the end of the period (b), the peripheral unit 3 cannot secure the bus right during the period (b). It is like this.

Next, the operation of the control device according to this embodiment will be described by dividing it into a normal bus access process, a process in which the CPU unit collectively secures a bus, and a process when bus requests occur simultaneously.

(1) Normal Bus Access Processing FIG. 3 is a flow chart showing the processing of the peripheral unit 3 that has become the bus master.

When transferring data to the CPU unit or another peripheral unit 3, the peripheral unit 3 determines whether or not the data transfer amount is larger than a predetermined upper limit value (step 310).

When the data transfer amount is larger than the predetermined upper limit value (step 310; y), the peripheral unit 3 divides the transfer data into a size equal to or smaller than the upper limit value and stores the divided data in the shared memory. (Step 320), the arbiter circuit 11 is requested to use the system bus 4 (step 330). On the other hand, if it is smaller than the upper limit value (step 310; n), a bus request is immediately requested to the arbiter circuit 11 (step 310). 330).

After that, the peripheral unit 3 judges whether or not the use permission of the system bus 4 is received from the arbiter circuit 11 (step 340). As a result, peripheral unit 3
If it is determined that the arbiter circuit 11 does not permit the use of the system bus 4 (step 340; n),
While returning to step 330 and performing the same processing, when it is determined that the system bus 4 is permitted to be used by the arbiter circuit 11 (step 340; y), the system bus 4
The data is transferred to the CPU unit 2 or the corresponding peripheral unit 3 via (step 350).

When the transfer amount is less than the upper limit value, the transfer data is transferred as it is, and when the transfer amount is equal to or more than the upper limit value, the upper limit stored in the shared memory 23 as described above. It is data divided into magnitudes of values.

When the peripheral unit 3 finishes transferring the data, the arbiter circuit 11 withdraws the request for using the system bus 4 and releases the bus (step 360).

Subsequently, the peripheral unit 3 determines whether or not all the transfer data stored in the shared memory 23 have been transferred in the next cycle (step 37).
0).

When all the transfer data has not been transferred (step 370; n), the peripheral unit 3 returns the process to step 330 and performs the same process as described above, while the transfer of all transfer data is completed. In this case (step 370; y), the execution of this normal bus access process is terminated.

As described above, when the CPU unit 2 is the bus master, the same processing is performed except for the processing of steps 310 and 320, and therefore the description of the processing will be omitted.

As described above, when the transfer amount of the data transferred by the peripheral unit 3 is larger than the predetermined upper limit value, the data is divided into the upper limit values and transferred in several times.
The data transfer time from the peripheral unit becomes uniform, and as a result, the time required for one cycle of the CPU unit 2 becomes uniform, and variations in cycle processing time can be eliminated.

(2) Processing for collectively securing bus by CPU unit FIG. 4 is a flowchart showing processing for collectively securing bus by CPU unit.

This process is a process executed during a period in which the system bus 4 is used very frequently during the processing of the CPU unit 2 (peripheral unit service execution period).

When the CPU unit 2 finishes executing the CPU user program (step 410), it issues a request to use the system bus 4 to the arbiter circuit 11 (step 4).
20) It is determined whether or not the bus use permission is obtained from the arbiter circuit 11 for a predetermined period (step 430).

When the CPU unit 2 does not obtain the bus use permission from the arbiter circuit 11 (step 430;
n), returning to step 420, the bus use request is issued to the arbiter circuit 11 again. On the other hand, when the bus use permission is obtained (step 430; y), a necessary series of bus access processing (step 440), for example, The execution instruction and the like are output to the peripheral unit 3.

Thereafter, the CPU unit 2 withdraws the bus use request from the arbiter circuit 11 and releases the bus (step 450).

As described above, during the period in which the CPU unit 2 is used at a very high frequency, the arbiter circuit 11 is continuously requested to use the bus until this series of processing is completed, so that the bus access is performed. The bus acquisition processing is not required for each processing, the processing is made efficient, and the cycle processing time can be reduced.

(3) Processing when bus requests are generated simultaneously FIG. 5 is a flowchart showing processing when bus requests are generated simultaneously.

This timing chart roughly divides the period according to the presence / absence of a bus request from the CPU unit 2. For example, during the period (a) and the period (c), the CPU unit 2
The bus request is OFF, and the periods (b) and (d) are ON.

First, when the peripheral unit 1 of # 1 and the peripheral unit 2 of # 2 simultaneously output a bus request to the arbiter circuit 11 (and reference), the peripheral unit 3 of # 1.
The peripheral unit 3 having a higher priority than the peripheral unit 3 of # 2 receives the bus right from the arbiter circuit 11 to acquire the bus right, and executes a predetermined process (see).

After that, when the peripheral unit 1 of # 1 releases the bus request, the peripheral unit 3 of # 2, which has received the bus use permission from the arbiter circuit 11, acquires the bus right (see) and performs a predetermined process. Run.

Subsequently, the CPU unit 2 makes a bus request to the arbiter circuit 11 (see), and the arbiter circuit 11
When the bus permission is received from (see), the bus right is acquired (see), a predetermined process is executed, and when the process is finished, the bus request is withdrawn (see).

Here, the peripheral unit 3 of # 1 is a CPU
If a bus request is issued while the unit 2 is permitting use of the bus, that is, while holding the bus right (see),
After the CPU unit 2 abandons the bus right, it acquires the bus right and executes a predetermined process to abandon the bus right (see a and b).

After that, before the CPU unit 2 requests the arbiter circuit 11 to use the bus, the peripheral unit 3 of # 2 is used.
When the bus request is issued to the arbiter circuit 11 (see c), the bus permission is obtained from the arbiter circuit 11 to obtain the bus right, the predetermined processing is executed, and the bus right is abandoned (see d and e).

Here, even if the CPU unit 2 requests the arbiter circuit 11 to use the bus while the peripheral unit 2 of # 2 holds the bus right (see f), the peripheral unit 3 of # 2.
Until he relinquishes the bus right, he does not get the bus license and therefore cannot obtain the bus right (see g and h).

As described above, the CPU unit 2 causes a waiting time until the peripheral unit releases the bus.
Since the upper limit value of the data transfer amount of the bus access processing time of the peripheral unit is constant, the variation of the cycle time can be made constant.

[0052]

As described above, according to the present invention, when the CPU unit or the peripheral unit determines that each transfer data amount is equal to or more than the upper limit value, a plurality of transfer data are provided for each upper limit value. Since data is transferred in cycles, the data transfer processing time becomes uniform, and the variation in cyclic processing can be reduced.

Further, when the CPU unit performs bus access processing with high frequency, the bus right is secured until this series of processing is completed, so it is not necessary to perform sequential bus access processing, and the cycle processing time is reduced. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a control device according to the present invention.

FIG. 2 is an explanatory diagram illustrating a cyclic process of the control device of this embodiment.

FIG. 3 is a flowchart showing a bus access process during the cyclic process of this embodiment.

FIG. 4 is a flowchart showing a process of collectively securing a bus during the cyclic process of this embodiment.

FIG. 5 is a timing chart showing the processing timing of the control device of this embodiment.

FIG. 6 is a block diagram showing a configuration of a control device having a conventional multi-bus master configuration.

FIG. 7 is a flowchart showing processing of a control device having a conventional multi-bus master configuration.

[Explanation of symbols]

 1 base unit 2 CPU unit 3 peripheral unit (I / O unit) 4 system bus 11 arbiter circuit 21,31 MPU 22,32 bus I / F 23,33 shared memory

Claims (3)

[Claims] 1. A control device comprising a CPU unit, a plurality of peripheral units that can be a bus master, and an arbiter circuit, wherein the CPU unit performs cyclic processing, wherein the CPU unit performs bus access processing at high frequency. In this case, the bus right securing means for securing the bus until this series of processing is completed, the peripheral unit is the second upper limit value setting means for setting the upper limit value of the transfer data amount, and the transfer data amount is the above. Second data amount determining means for determining whether or not the transfer data amount is greater than the upper limit value set by the second upper limit value setting means, and the second data amount determining means determines the transfer data amount by the second upper limit. If it is determined that the value is greater than or equal to the upper limit value set by the value setting means, the transfer data is transferred for each upper limit value in a plurality of cycles while the transfer data amount is increased. When it is determined that the value is less than the upper limit value set by the second upper limit value setting means, a second data transfer means for transferring this data as it is, a control device comprising: 2. The arbiter circuit according to claim 1, wherein the CPU unit acquires the bus right when the CPU unit and the peripheral unit compete with each other when a bus use request occurs. Control device. 3. The arbiter circuit is provided for the CPU when the bus use requests from the peripheral units conflict with each other.
The bus right is acquired by a peripheral unit connected to a position close to the unit.
The control device described.